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freescale semiconductor data sheet: technical data document number: mpc5668x rev. 5, 01/2011 ? freescale semiconductor, inc., 2010, 2011. all rights reserved. this document contains information on a prod uct under development. freescale reserves the right to change or discontinue this product without notice. mpc5668x mapbga?208 17 mm x 17 mm mapbga?256 17 mm x 17 mm mpc5668x features: ? 32-bit cpu core complex (e200z650) ? compliant with power architecture embedded category ? 32 kb unified cache with line locking and eight-entry store buffer16 ? execution speed static to 116 mhz ? 32-bit i/o processor (e200z0) ? execution speed static to 1/2 cpu core speed (58 mhz) ? 2 mb on-chip flash ? supports read during program and erase operations, and multiple blocks allowing eeprom emulation ? 512 kb + 80 kb (592 kb) on-chip ecc sram (mpc5668g) ? 128 kb on-chip ecc sram (MPC5668E) ? 16-entry memory protection unit (MPC5668E only) ? direct memory access controller ? 16-channel on mpc5668g ? 32-channel on MPC5668E ? fast ethernet controller ? supports 10-mbps and 100-mbps ieee 802.3 mii, 10-mbps 7-wire interface ? ieee 802.3 mac (complia nt with ieee 802.3 1998 edition) ? media local bus (mlb) interface (mpc5668g only) ? supports 16 logical channels, max speed 1024 fs ? interrupt controller (intc) supports 316 external interrupt vectors (22 are reserved) ? system clocks ? frequency-modulated phase-locked loop (fmpll) ? 4?40mhz crystal oscillator (xtal) ? 32 khz crystal oscillator (xtal) ? dedicated 16 mhz and 128 khz internal rc oscillators ? analog to digital converter (adc) module ? 10-bit a/d resolution ? 32 external channels ? 36 internal channels (mpc5668g) ? 64 internal channels (MPC5668E) ? cross-triggering unit (MPC5668E only) ? internal conversion triggering for adc ? triggerable by internal timers or emios200 ? deserial serial periph eral interface (dspi) ? four individual dspi modules ? full duplex, synchronous transfers ? master or slave operation ? inter-ic communication (i 2 c) interface ? four individual i 2 c modules ? multi-master operation ? serial communication interface (esci) module ? two-channel dma interface ? configurable as lin bus master ? emios200 timed input/output ? 24 channels, 16-bit timers (mpc5668g) ? 32 channels, 16-bit timers (MPC5668E) ? controller area network (flexcan) module ? compliant with can protocol specification, version 2.0b active ? 64 mailboxes, each configurab le as transmit or receive ? dual-channel flexray controller ? full implementation of flexray protocol specification 2.1, reva ? 128 message buffers ? jtag controller (mpc5668g only) ? compliant with the ieee 1149.1-2001 ? nexus development interface (ndi) ? available in 256 mapbga package only ? compliant with ieee-isto 5001-2003 ? nexus class 3 development support on e200z650 ? nexus class 2+ development support on e200z0 ? internal voltage regulator allows operation from single 3.3 v or 5 v supply mpc5668x microcontroller data sheet
mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 2 table of contents 1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 orderable parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 mpc5668x block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.1 208-ball mapbga pin assignments . . . . . . . . . . . . . . . .6 3.2 256-ball mapbga pin assignments . . . . . . . . . . . . . . . .7 3.3 pin muxing and reset states . . . . . . . . . . . . . . . . . . . . .8 3.3.1 power and ground supply summary . . . . . . . .25 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .27 4.2.1 general notes for specifications at maximum junction temperature . . . . . . . . . . . . . . . . . . . .27 4.3 esd characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.4 vrc electrical specifications . . . . . . . . . . . . . . . . . . . .30 4.5 dc electrical specifications . . . . . . . . . . . . . . . . . . . . .30 4.6 operating current specifications . . . . . . . . . . . . . .32 4.7 i/o pad current specifications . . . . . . . . . . . . . . . . . . .34 4.7.1 i/o pad v dd33 current specifications . . . . . . . .35 4.8 low voltage characteristics . . . . . . . . . . . . . . . . . . . . 36 4.9 oscillators electrical characteri stics . . . . . . . . . . . . . . 36 4.10 fmpll electrical characteristics. . . . . . . . . . . . . . . . . 38 4.11 adc electrical characteristics. . . . . . . . . . . . . . . . . . . 39 4.12 flash memory electrical charac teristics . . . . . . . . . . . 39 4.13 pad ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.14 ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.14.1 reset and boot configuration pins . . . . . . . . . 43 4.14.2 external interrupt (irq) and non-maskable interrupt (nmi) pins . . . . . . . . . . . . . . . . . . . . . 43 4.14.3 jtag (ieee 1149.1) interface . . . . . . . . . . . . . 44 4.14.4 nexus debug interface. . . . . . . . . . . . . . . . . . . 47 4.14.5 enhanced modular i/o subsystem (emios) . . 49 4.14.6 deserial serial peripheral interface (dspi) . . . 50 4.14.7 mlb interface . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.14.8 fast ethernet interface . . . . . . . . . . . . . . . . . . 57 5 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . 61 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 1. mpc5668g/MPC5668E comparison feature mpc5668g MPC5668E package 208 mapbga 256 mapbga 208 mapbga 256 mapbga ram with ecc 592 kb 128 kb mpu no 16 entry dma 16-channel 32-channel ethernet (fec) yes no medialb (mlb-dim) yes no flexray yes (128 message buffers) no adc (10-bit) 36 internal channels supports 32 external channels 64 internal channels supports 32 external channels total timer i/o (emios200) 24 channels, 16-bit 32 channels, 16-bit cross trigger unit (ctu) no yes sci (esci) 6 12 spi (dspi) 4 4 can (flexcan) 6 5 i 2 c44 nexus3 debug (e200z6) nexus2+ debug (e200z0) ? supported on 256bga emulation package ? supported on 256bga emulation package
ordering information mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 3 1 ordering information 1.1 orderable parts table 1 shows the orderable part numbers for the mpc5668x. table 1. orderable part numbers freescale part number 1 1 all packaged devices are ppc5668 x , rather than mpc5668 x or spc5668 x , until product qualifications are complete. the unpackaged device prefix is pcc, rather than scc, until product qualification is complete. not all configurations are available in the ppc parts. package description speed (mhz) operat ing temperature 2 2 the lowest ambient operating temperature (t a ) is referenced by t l ; the highest ambient operating temperature is referenced by t h . max 3 (f max ) 3 maximum speed is the maximum frequency al lowed including frequency modulation (fm). min (t l ) max (t h ) spc5668gf0avmg mpc5668 g 208 mapbga package lead-free (pbfree) 116 ?40 c 105 c spc5668gf0avmj 4 4 the 256 mapbga package for the mpc5668x is not intended for fu ll production qualification, and is supplied for development use only. mpc5668g 256 mapbga package lead-free (pbfree) 116 ?40 c 105 c spc f mg r qualification status core code device number fabrication site revision temperature range package identifier tape and reel status temperature range c = ?40 c to 85 c v = ?40c to 105c package identifier mg = 208 mapbga pb-free mj = 256 mapbga pb-free core code pc = power architecture tape and reel status r = tape and reel (blank) = trays qualification status p = prototype m = fully spec. qualified, general market flow s = fully spec. qualified, automotive flow note: not all options are available on all devices. refer to ta b l e 1 . 5668g 0a v fabrication site f = freescale
mpc5668x microcontrolle r data sheet, rev. 5 mpc5668x block diagrams freescale semiconductor 4 2 mpc5668x block diagrams figure 1 shows a top-level block diagram of the mpc5668g device. figure 1. mpc5668g block diagram adc ? analog to digital converter bam ? boot assist module dspi ? serial peripherals interface ecc ? error correction code ecsm ? error correction status module emios ? timed input output edma ? enhanced direct memory access controller esci ? serial communications interface fec ? fast ethernet controller flexcan ? controller area network controller flexray? ? flexray bus controller fmpll ? frequency modulated phase locked loop 4?40 mhz spp crossbar switch (xbar) fmpll e200z650 core 32k cache 16chdma 16 mhz fpu/spe vle mmu(32tlb) legend e200z0 core vle masters mux flash (ecc) sram (ecc) 512 kb 2 mb aips(0) bridge b 6 x esci 36 x adc 2 x i 2 c 2 x dspi 24 x emios 6 x flexcan jtag ndi nexus3(z6) debug ndi nexus2+(z0) aips(1) bridge a 2 x i 2 c 2 x dspi vreg 4/8 way fec mlb-dim flexray controller irc xtal mpc5668g standby ram sram (ecc) 80 kb i 2 c ? inter ic controller intc ? interrupt controller jtag ? joint test action group interface mlb-dim ? media local bus device interface module ndi ? nexus debug interface pit ? periodic interrupt timer rtc ? real time clock siu ? system integration stm ? system timer module swt ? software watchdog timer vreg ? voltage regulator 128 khz irc 32 khz xtal swt intc siu pit bam rtc/api stm ecsm ecsm ecsm semaphores
mpc5668x block diagrams mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 5 figure 2 shows a top level block diagram for the MPC5668E device. figure 2. MPC5668E block diagram i 2 c ? inter ic controller intc ? interrupt controller jtag ? joint test action group interface mpu ? memory protection unit ndi ? nexus debug interface pit ? periodic interrupt timer rtc ? real time clock siu ? system integration stm ? system timer module swt ? software watchdog timer vreg ? voltage regulator adc ? analog to digital converter bam ? boot assist module ctu ? cross triggering unit dspi ? serial peripherals interface controller ecc ? error correction code ecsm ? error correction status module edma ? enhanced direct memory access controller emios200 ? timed input output esci ? serial communications interface flexcan ? controller area network controller fmpll ? frequency modulated phase locked loop 4?40 mhz spp crossbar switch (xbar) fmpll e200z650 core 32k cache 16 mhz 128 khz fpu/spe vle mmu(32tlb) legend 32 khz e200z0 core vle masters mux memory protection unit (mpu) flash (ecc) sram (ecc) 128 kb 2 mb aips(0) bridge b 64 x adc 32 x emios 5 x flexcan 2 x dspi 8 x esci ctu 2 x i 2 c jtag ndi nexus3(z6) debug ndi nexus2+(z0) aips(1) bridge a 4 x esci 2 x i 2 c 2 x dspi swt vreg intc siu pit bam rtc/api stm 4/8 way controller irc xtal xtal irc MPC5668E standby ram semaphores 32chdma standby ram ecsm ecsm
mpc5668x microcontrolle r data sheet, rev. 5 pin assignments freescale semiconductor 6 3 pin assignments 3.1 208-ball mapbga pin assignments figure 3 shows the 208-ball mapbga pin assignments. figure 3. mpc5668x 208-ball mapbga (full diagram) note: this ballmap is preliminary and should not be used for board design. v dd33 test v dd 1 2 3 4 5 6 7 8 9 10111213141516 v dda pa8 v ssa pb14 pb6 pc3 pc7 pc10 v rcctl v dd a v dd v rh v rl pa12 pb0 pb5 pc0 pc4 pc8 pc11 pc12 b v ss pa9 pa11 pa15 pb1 pb4 pb7 pc1 pc5 pc9 v ss pc13 pc14 c v ss pa10 pa14 pb11 v dde1 v ss pd0 pd1 d pd2 pd3 pd4 e pd6 pd7 pd9 f pd8 g v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss pe6 h v ss v ss v ss v ss pe9 pd14 j pd15 pe0 k pe1 l m v ss pf0 v ss n pg3 pf1 extal p pg5 pf2 tdi r v dd pg6 t a b c d e f g h j k l m 1 2 3 4 5 6 7 8 9 10111213141516 pa13 208 mapbga ball map (as viewed from top through the package) n p r t pb9 pb8 pd10 pd11 pa6 pa3 reset pk0 pa7 pa5 pb3 pd13 pd12 pe7 pa4 pa0 pg7 xtal tms pc6 pd5 pe2 v sssyn pj2 v dde3 pa1 pa2 pj13 pj14 pj15 pj12 ph5 ph6 ph7 pj8 pj9 v dde2 ph0 ph2 pg13 pg14 pg9 pg10 pg11 pg0 pj4 pf7 pf11 pj6 pg2 pf13 pj3 pj7 pf10 pg1 pf4 pf9 pj5 tdo v ddsyn pb12 pb15 pb13 pb10 pc2 pb2 pc15 v rcsel v rc pk9 pk7 pk8 pk5 pk6 pk3 pk4 pe3 pe8 pe5 pe4 pj0 pj1 pe11 pe10 pe14 v ss pf3 pe15 pf12 ph11 ph9 pj10 ph3 pg15 ph15 pf6 v dde4 v dd pk1 jcomp v dd pg4 pg12 pg8 v ddemlb pk2 pe12 pe13 tck pf15 ph10 pf14 pf8 ph12 ph13 pj11 ph4 ph1 pf5 ph14 ph8 pk10
pin assignments mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 7 3.2 256-ball mapbga pin assignments figure 4 shows the 256-ball mapbga pin assignments. figure 4. mpc5668x 256-ball mapbga (full diagram) note: this ballmap is preliminary and should not be used for board design. test v dd33 v dde3 v ss v ss v ss pa9 pa11 pa15 pd7 pd8 pe0 pe1 pa1 v ddenex mdo0 v ss v ss v ss v ss v ss v ss v dd v dda pa8 v ssa pb14 pb6 pc3 pc7 pc10 v dd v dd v rh v rl pa12 pb0 pb5 pc0 pc4 pc8 pc11 pc12 v ss pb1 pb4 pb7 pc1 pc5 pc9 v ss pc13 pc14 v ss pa10 pa14 pb11 v dde1 v ss pd0 pd1 pd2 pd3 pd4 pd6 pd9 v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss pe6 v ss v ss v ss v ss pe9 pd14 pd15 v ss pf0 v ss pg3 pf1 extal pg5 pf2 tdi v dd pg6 pa13 pb9 pb8 pd10 pd11 pa6 pa3 reset pk0 pa7 pa5 pb3 pd13 pd12 pe7 pa4 pa0 xtal tms pc6 pd5 pe2 v sssyn pj2 pa2 pj13 pj14 pj15 pj12 ph5 ph6 ph7 pj8 pj9 v dde2 ph0 ph2 pg13 pg14 pg9 pg10 pg11 pg0 pj4 pf7 pf11 pj6 pg2 pf13 pj3 pj7 pf10 pg1 pf4 pf9 pj5 tdo v ddsyn pb12 pb15 pb13 pb10 pc2 pb2 pc15 v rcsel pk9 pk7 pk8 pk5 pk6 pk3 pk4 pe3 pe8 pe5 pe4 pj0 pj1 pe11 pe10 pe14 v ss pf3 pe15 pf12 ph11 ph9 pj10 ph3 pg15 ph15 pf6 v dde4 v dd pk1 jcomp v dd pg4 pg12 pg8 v ddemlb pk2 pe12 pe13 tck pf15 ph10 pf14 pf8 ph12 ph13 pj11 ph4 ph1 pf5 ph14 ph8 pk10 pg7 v ddenex v ddenex v rcctl v rc mseo0 mdo4 mdo3 mdo2 mdo1 mdo11 mdo10 mdo8 mdo9 mdo7 mdo5 mdo6 mseo1 mcko evti evto v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss 256 mapbga ball map (as viewed from top through the package) 1 2 3 4 5 6 7 8 9 10111213141516 a b c d e f g h j k l m n p r t a b c d e f g h j k l m 1 2 3 4 5 6 7 8 9 10111213141516 n p r t
mpc5668x microcontrolle r data sheet, rev. 5 pin assignments freescale semiconductor 8 3.3 pin muxing and reset states table 2 shows the signals properties for each pin on mpc5668x. for all port pins that have an associated siu_pcr n register to control pin properties, the supported functions column lis ts the functions associated with the programming of the siu_pcr n [pa] bit in the order: general-purpose input/output (gpio), function 1, func tion 2, and function 3 (see figure 5 ). when an alternate functi on is not implemented for a value of siu_pcr n [pa], a dash is shown in the description column and the respective value in the pa bitfield is reserved. figure 5. supported functions example table 2. mpc5668x signal properties pin name 1 supported functions 2 gpio (pcr) num 3 pa 4 description i/o type volt- age pad type 5 status package pin locations during reset 6 after reset 7 208 bga 256 bga port a (16) pa 0 pa [ 0 ] an[0] 000 01 10 11 port a gpi adc analog input ? ? i i ? ? v dda iha ? ? d15 d15 pa 1 pa [ 1 ] an[1] 100 01 10 11 port a gpi adc analog input ? ? i i ? ? v dda iha ? ? e15 e15 pa 2 pa [ 2 ] an[2] 200 01 10 11 port a gpi adc analog input ? ? i i ? ? v dda iha ? ? f16 f16 pa 3 pa [ 3 ] an[3] 300 01 10 11 port a gpi adc analog input ? ? i i ? ? v dda iha ? ? f15 f15 pa 4 pa [ 4 ] an[4] 400 01 10 11 port a gpi adc analog input ? ? i i ? ? v dda iha ? ? g16 g16 pa 5 pa [ 5 ] an[5] 500 01 10 11 port a gpi adc analog input ? ? i i ? ? v dda iha ? ? g15 g15 pa [ 0 ] an[0] gpio function 1 functions 2 and 3 not implemented 000 01 10 11 supported functions 2 gpio (pcr) num 3 pa 4 description port a gpi adc analog input ? ?
pin assignments mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 9 pa 6 pa [ 6 ] an[6] 600 01 10 11 port a gpi adc analog input ? ? i i ? ? v dda iha ? ? h16 h16 pa 7 pa [ 7 ] an[7] 700 01 10 11 port a gpi adc analog input ? ? i i ? ? v dda iha ? ? g14 g14 pa 8 pa [ 8 ] an[8] 800 01 10 11 port a gpi adc analog input ? ? i i ? ? v dda iha ? ? f14 f14 pa 9 pa [ 9 ] an[9] 900 01 10 11 port a gpi adc analog input ? ? i i ? ? v dda iha ? ? e14 e14 pa10 pa[10] an[10] 10 00 01 10 11 port a gpi adc analog input ? ? i i ? ? v dda iha ? ? d13 d13 pa11 pa[11] an[11] 11 00 01 10 11 port a gpi adc analog input ? ? i i ? ? v dda iha ? ? e13 e13 pa12 pa[12] an[12] 12 00 01 10 11 port a gpi adc analog input ? ? i i ? ? v dda iha ? ? d14 d14 pa13 pa[13] an[13] 13 00 01 10 11 port a gpi adc analog input ? ? i i ? ? v dda iha ? ? f13 f13 pa14 pa[14] an[14] extal32 14 00 01 10 11 port a gpi adc analog input external 32 khz crystal in ? i i i ? v dda iha ? ? d16 d16 pa15 pa[15] an[15] xtal32 15 00 01 10 11 port a gpi adc analog input external 32 khz crystal out ? i i o ? v dda iha ? ? e16 e16 table 2. mpc5668x signal properties (continued) pin name 1 supported functions 2 gpio (pcr) num 3 pa 4 description i/o type volt- age pad type 5 status package pin locations during reset 6 after reset 7 208 bga 256 bga
mpc5668x microcontrolle r data sheet, rev. 5 pin assignments freescale semiconductor 10 port b (16) pb0 pb[0] an[16]/anw 16 00 01 10 11 port b gpio adc analog input/mux in ? ? i/o i ? ? v dde1 sha ? ? b14 b14 pb1 pb[1] an[17]/anx 17 00 01 10 11 port b gpio adc analog input/mux in ? ? i/o i ? ? v dde1 sha ? ? c14 c14 pb2 pb[2] an[18]/any 18 00 01 10 11 port b gpio adc analog input/mux in ? ? i/o i ? ? v dde1 sha ? ? b13 b13 pb3 pb[3] an[19]/anz 19 00 01 10 11 port b gpio adc analog input/mux in ? ? i/o i ? ? v dde1 sha ? ? c13 c13 pb4 pb[4] an[20] 20 00 01 10 11 port b gpio adc analog input ? ? i/o i ? ? v dde1 sha ? ? c12 c12 pb5 pb[5] an[21] 21 00 01 10 11 port b gpio adc analog input ? ? i/o i ? ? v dde1 sha ? ? d12 d12 pb6 pb[6] an[22] 22 00 01 10 11 port b gpio adc analog input ? ? i/o i ? ? v dde1 sha ? ? c11 c11 pb7 pb[7] an[23] 23 00 01 10 11 port b gpio adc analog input ? ? i/o i ? ? v dde1 sha ? ? d11 d11 pb8 pb[8] an[24] pcs_a[2] 24 00 01 10 11 port b gpio adc analog input dspi_a peripheral chip select ? i/o i o ? v dde1 sha ? ? a10 a10 pb9 pb[9] an[25] pcs_a[3] 25 00 01 10 11 port b gpio adc analog input dspi_a peripheral chip select ? i/o i o ? v dde1 sha ? ? b12 b12 table 2. mpc5668x signal properties (continued) pin name 1 supported functions 2 gpio (pcr) num 3 pa 4 description i/o type volt- age pad type 5 status package pin locations during reset 6 after reset 7 208 bga 256 bga
pin assignments mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 11 pb10 pb[10] an[26] pcs_b[4] 26 00 01 10 11 port b gpio adc analog input dspi_b peripheral chip select ? i/o i o ? v dde1 sha ? ? a9 a9 pb11 pb[11] an[27] pcs_b[5] 27 00 01 10 11 port b gpio adc analog input dspi_b peripheral chip select ? i/o i o ? v dde1 sha ? ? b9 b9 pb12 pb[12] an[28] pcs_c[1] 28 00 01 10 11 port b gpio adc analog input dspi_c peripheral chip select ? i/o i o ? v dde1 sha ? ? c10 c10 pb13 pb[13] an[29] pcs_c[2] 29 00 01 10 11 port b gpio adc analog input dspi_c peripheral chip select ? i/o i o ? v dde1 sha ? ? a8 a8 pb14 pb[14] an[30] pcs_d[3] 30 00 01 10 11 port b gpio adc analog input dspi_d peripheral chip select ? i/o i o ? v dde1 sha ? ? b8 b8 pb15 pb[15] an[31] pcs_d[4] 31 00 01 10 11 port b gpio adc analog input dspi_d peripheral chip select ? i/o i o ? v dde1 sha ? ? c9 c9 port c (16) pc0 pc[0] an[32] 32 00 01 10 11 port c gpio adc analog input ? ? i/o i ? ? v dde1 sha ? ? d9 d9 pc1 pc[1] an[33] 33 00 01 10 11 port c gpio adc analog input ? ? i/o i ? ? v dde1 sha ? ? c8 c8 pc2 pc[2] an[34] evti 34 00 01 10 11 port c gpio adc analog input nexus event in ? i/o i i ? v dde1 sha ? ? a7 a7 pc3 pc[3] an[35] evto 35 00 01 10 11 port c gpio adc analog input nexus event out ? i/o i o ? v dde1 sha ? ? b7 b7 table 2. mpc5668x signal properties (continued) pin name 1 supported functions 2 gpio (pcr) num 3 pa 4 description i/o type volt- age pad type 5 status package pin locations during reset 6 after reset 7 208 bga 256 bga
mpc5668x microcontrolle r data sheet, rev. 5 pin assignments freescale semiconductor 12 pc4 pc[4] an[36] 36 00 01 10 11 port c gpio adc analog input ? ? i/o i ? ? v dde1 sha ? ? d8 d8 pc5 pc[5] an[37] z6nmi 37 00 01 10 11 port c gpio adc analog input z6 core non-ma skable interrupt ? i/o i i ? v dde1 sha ? ? c6 c6 pc6 pc[6] an[38] z0nmi 38 00 01 10 11 port c gpio adc analog input z0 core non-ma skable interrupt ? i/o i i ? v dde1 sha ? ? c7 c7 pc7 pc[7] an[39] fr_dbg3 39 00 01 10 11 port c gpio adc analog input flexray debug ? i/o i o ? v dde1 sha ? ? a6 a6 pc8 pc[8] an[40] fr_dbg2 40 00 01 10 11 port c gpio adc analog input flexray debug ? i/o i o ? v dde1 sha ? ? b6 b6 pc9 pc[9] an[41] fr_dbg1 41 00 01 10 11 port c gpio adc analog input flexray debug ? i/o i o ? v dde1 sha ? ? a5 a5 pc10 pc[10] an[42] fr_dbg0 42 00 01 10 11 port c gpio adc analog input flexray debug ? i/o i o ? v dde1 sha ? ? b5 b5 pc11 pc[11] an[43] scl_c ? 43 00 01 10 11 port c gpio adc analog input i 2 c_c serial clock ? i/o i i/o ? v dde1 sha ? ? b4 b4 pc12 pc[12] an[44] sda_c ? 44 00 01 10 11 port c gpio adc analog input i 2 c_c serial data ? i/o i i/o ? v dde1 sha ? ? a4 a4 pc13 pc[13] an[45] ? ma[0] 45 00 01 10 11 port c gpio adc analog input ? adc ext. mux address select i/o i ? o v dde1 sha ? ? c5 c5 pc14 pc[14] an[46] ma[1] ? 46 00 01 10 11 port c gpio adc analog input adc ext. mux address select ? i/o i ? o v dde1 sha ? ? c4 c4 table 2. mpc5668x signal properties (continued) pin name 1 supported functions 2 gpio (pcr) num 3 pa 4 description i/o type volt- age pad type 5 status package pin locations during reset 6 after reset 7 208 bga 256 bga
pin assignments mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 13 pc15 pc[15] an[47] ma[2] ? 47 00 01 10 11 port c gpio adc analog input adc ext. mux address select ? i/o i o ? v dde1 sha ? ? d5 d5 port d (16) pd0 pd[0] cntx_a 48 00 01 10 11 port d gpio flexcan_a transmit ? ? i/o o ? ? v dde2 sh ? ? a2 a2 pd1 pd[1] cnrx_a 49 00 01 10 11 port d gpio flexcan_a receive ? ? i/o i ? ? v dde2 sh ? ? b2 b2 pd2 pd[2] cntx_b 50 00 01 10 11 port d gpio flexcan_b transmit ? ? i/o o ? ? v dde2 sh ? ? b1 b1 pd3 pd[3] cnrx_b 51 00 01 10 11 port d gpio flexcan_b receive ? ? i/o i ? ? v dde2 sh ? ? c1 c1 pd4 pd[4] cntx_c 52 00 01 10 11 port d gpio flexcan_c transmit ? ? i/o o ? ? v dde2 sh ? ? c2 c2 pd5 pd[5] cnrx_c 53 00 01 10 11 port d gpio flexcan_c receive ? ? i/o i ? ? v dde2 sh ? ? d1 d1 pd6 pd[6] cntx_d txd_k scl_b 54 00 01 10 11 port d gpio flexcan_d transmit sci_k transmit i 2 c_b serial clock i/o o o i/o v dde2 sh ? ? d2 d2 pd7 pd[7] cnrx_d rxd_k sda_b 55 00 01 10 11 port d gpio flexcan_d receive sci_k receive i 2 c_b serial data i/o i i i/o v dde2 sh ? ? e1 e1 pd8 pd[8] cntx_e txd_l scl_c 56 00 01 10 11 port d gpio flexcan_e transmit sci_l transmit i 2 c_c serial clock i/o o o i/o v dde2 sh ? ? e2 e2 table 2. mpc5668x signal properties (continued) pin name 1 supported functions 2 gpio (pcr) num 3 pa 4 description i/o type volt- age pad type 5 status package pin locations during reset 6 after reset 7 208 bga 256 bga
mpc5668x microcontrolle r data sheet, rev. 5 pin assignments freescale semiconductor 14 pd9 pd[9] cnrx_e rxd_l sda_c 57 00 01 10 11 port d gpio flexcan_e receive sci_l receive i 2 c_c serial data i/o i i i/o v dde2 sh ? ? f1 f1 pd10 pd[10] cntx_f txd_m scl_d 58 00 01 10 11 port d gpio flexcan_f transmit sci_m transmit i 2 c_d serial clock i/o o o i/o v dde2 sh ? ? f2 f2 pd11 pd[11] cnrx_f rxd_m sda_d 59 00 01 10 11 port d gpio flexcan_f receive sci_m receive i 2 c_d serial data i/o i i i/o v dde2 sh ? ? g1 g1 pd12 pd[12] txd_a 60 00 01 10 11 port d gpio esci_a transmit ? ? i/o o ? ? v dde2 sh ? ? g2 g2 pd13 pd[13] rxd_a 61 00 01 10 11 port d gpio esci_a receive ? ? i/o i ? ? v dde2 sh ? ? h1 h1 pd14 pd[14] txd_b 62 00 01 10 11 port d gpio esci_b transmit ? ? i/o o ? ? v dde2 sh ? ? c3 c3 pd15 pd[15] rxd_b 63 00 01 10 11 port d gpio esci_b receive ? ? i/o i ? ? v dde2 sh ? ? d3 d3 port e (16) pe0 pe[0] txd_c emios[31] 64 00 01 10 11 port e gpio esci_c transmit emios channel ? i/o o i/o ? v dde2 sh ? ? e3 e3 pe1 pe[1] rxd_c emios[30] 65 00 01 10 11 port e gpio esci_c receive emios channel ? i/o i i/o v dde2 sh ? ? e4 e4 pe2 pe[2] txd_d emios[29] 66 00 01 10 11 port e gpio esci_d transmit emios channel ? i/o o i/o v dde2 sh ? ? f4 f4 table 2. mpc5668x signal properties (continued) pin name 1 supported functions 2 gpio (pcr) num 3 pa 4 description i/o type volt- age pad type 5 status package pin locations during reset 6 after reset 7 208 bga 256 bga
pin assignments mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 15 pe3 pe[3] rxd_d emios[28] 67 00 01 10 11 port e gpio esci_d receive emios channel ? i/o i i/o v dde2 sh ? ? f3 f3 pe4 pe[4] txd_e emios[27] 68 00 01 10 11 port e gpio esci_e transmit emios channel ? i/o o i/o v dde2 sh ? ? g3 g3 pe5 pe[5] rxd_e emios[26] 69 00 01 10 11 port e gpio esci_e receive emios channel ? i/o i i/o v dde2 sh ? ? h3 h3 pe6 pe[6] txd_f emios[25] 70 00 01 10 11 port e gpio esci_f transmit emios channel ? i/o o i/o v dde2 sh ? ? m2 m2 pe7 pe[7] rxd_f emios[24] 71 00 01 10 11 port e gpio esci_f receive emios channel ? i/o i i/o v dde2 sh ? ? l2 l2 pe8 pe[8] txd_g pcs_a[1] 72 00 01 10 11 port e gpio esci_g transmit dspi_a peripheral chip select ? i/o o o v dde2 sh ? ? j4 j4 pe9 pe[9] rxd_g pcs_a[4] 73 00 01 10 11 port e gpio esci_g receive dspi_a peripheral chip select ? i/o i o v dde2 sh ? ? m4 m4 pe10 pe[10] txd_h pcs_b[3] 74 00 01 10 11 port e gpio esci_h transmit dspi_b peripheral chip select ? i/o o o v dde2 sh ? ? n3 n3 pe11 pe[11] rxd_h pcs_b[2] 75 00 01 10 11 port e gpio esci_h receive dspi_b peripheral chip select ? i/o i o v dde2 sh ? ? n4 n4 pe12 pe[12] txd_j pcs_c[5] 76 00 01 10 11 port e gpio esci_j transmit dspi_c peripheral chip select ? i/o o o v dde2 sh ? ? p4 p4 pe13 pe[13] rxd_j pcs_c[3] 77 00 01 10 11 port e gpio esci_j receive dspi_c peripheral chip select ? i/o i o v dde2 sh ? ? p5 p5 table 2. mpc5668x signal properties (continued) pin name 1 supported functions 2 gpio (pcr) num 3 pa 4 description i/o type volt- age pad type 5 status package pin locations during reset 6 after reset 7 208 bga 256 bga
mpc5668x microcontrolle r data sheet, rev. 5 pin assignments freescale semiconductor 16 pe14 pe[14] scl_a pcs_d[2] 78 00 01 10 11 port e gpio i 2 c_a serial clock dspi_d peripheral chip select ? i/o i/o o ? v dde2 sh ? ? n7 n7 pe15 pe[15] sda_a pcs_d[5] 79 00 01 10 11 port e gpio i 2 c_a serial data dspi_d peripheral chip select ? i/o i/o o ? v dde2 sh ? ? n6 n6 port f (16) pf0 pf[0] sck_a 80 00 01 10 11 port f gpio dspi_a serial clock ? ? i/o i/o ? ? v dde2 mh ? ? h2 h2 pf1 pf[1] sout_a 81 00 01 10 11 port f gpio dspi_a serial data out ? ? i/o o ? ? v dde2 mh ? ? j1 j1 pf2 pf[2] sin_a 82 00 01 10 11 port f gpio dspi_a serial data in ? ? i/o i ? ? v dde2 sh ? ? j2 j2 pf3 pf[3] pcs_a[0] pcs_b[5] pcs_c[4] 83 00 01 10 11 port f gpio dspi_a peripheral chip select dspi_b peripheral chip select dspi_c peripheral chip select i/o i/o o o v dde2 sh ? ? n2 n2 pf4 pf[4] sck_b pcs_a[1] pcs_c[2] 84 00 01 10 11 port f gpio dspi_b serial clock dspi_a peripheral chip select dspi_c peripheral chip select i/o i/o o o v dde2 mh ? ? m1 m1 pf5 pf[5] sout_b pcs_a[2] pcs_c[3] 85 00 01 10 11 port f gpio dspi_b serial data out dspi_a peripheral chip select dspi_c peripheral chip select i/o o o o v dde2 mh ? ? p2 p2 pf6 pf[6] sin_b pcs_a[3] pcs_c[5] 86 00 01 10 11 port f gpio dspi_b serial data in dspi_a peripheral chip select dspi_c peripheral chip select i/o i o o v dde2 sh ? ? n1 n1 pf7 pf[7] pcs_b[0] pcs_c[5] pcs_d[4] 87 00 01 10 11 port f gpio dspi_b peripheral chip select dspi_c peripheral chip select dspi_d peripheral chip select i/o i/o o o v dde2 sh ? ? r2 r2 table 2. mpc5668x signal properties (continued) pin name 1 supported functions 2 gpio (pcr) num 3 pa 4 description i/o type volt- age pad type 5 status package pin locations during reset 6 after reset 7 208 bga 256 bga
pin assignments mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 17 pf8 pf[8] sck_c 88 00 01 10 11 port f gpio dspi_c serial clock ? ? i/o i/o ? ? v dde2 mh ? ? p1 p1 pf9 pf[9] sout_c 89 00 01 10 11 port f gpio dspi_c serial data out ? ? i/o o ? ? v dde2 mh ? ? t2 t2 pf10 pf[10] sin_c 90 00 01 10 11 port f gpio dspi_c serial data in ? ? i/o i ? ? v dde2 sh ? ? r1 r1 pf11 pf[11] pcs_c[0] pcs_d[5] pcs_a[4] 91 00 01 10 11 port f gpio dspi_c peripheral chip select dspi_d peripheral chip select dspi_a peripheral chip select i/o i/o o o v dde2 sh ? ? r3 r3 pf12 pf[12] sck_d 92 00 01 10 11 port f gpio dspi_d serial clock ? ? i/o i/o ? ? v dde3 mh ? ? n14 n14 pf13 pf[13] sout_d 93 00 01 10 11 port f gpio dspi_d serial data out ? ? i/o o ? ? v dde3 mh ? ? m14 m14 pf14 pf[14] sin_d 94 00 01 10 11 port f gpio dspi_d serial data in ? ? i/o i ? ? v dde3 sh ? ? p14 p14 pf15 pf[15] pcs_d[0] pcs_a[5] pcs_b[4] 95 00 01 10 11 port f gpio dspi_d peripheral chip select dspi_a peripheral chip select dspi_b peripheral chip select i/o i/o o o v dde3 sh ? ? p13 p13 port g (16) pg0 pg[0] pcs_a[4] pcs_b[3] an[48] 96 00 01 10 11 port g gpio dspi_a peripheral chip select dspi_b peripheral chip select adc analog input i/o o o i v dde2 sha ? ? b3 b3 pg1 pg[1] pcs_a[5] pcs_b[4] an[49] 97 00 01 10 11 port g gpio dspi_a peripheral chip select dspi_b peripheral chip select adc analog input i/o o o i v dde2 sha ? ? a3 a3 table 2. mpc5668x signal properties (continued) pin name 1 supported functions 2 gpio (pcr) num 3 pa 4 description i/o type volt- age pad type 5 status package pin locations during reset 6 after reset 7 208 bga 256 bga
mpc5668x microcontrolle r data sheet, rev. 5 pin assignments freescale semiconductor 18 pg2 pg[2] pcs_d[1] scl_c an[50] 98 00 01 10 11 port g gpio dspi_d peripheral chip select i 2 c_c serial clock adc analog input i/o o i/o i v dde3 sha ? ? h14 h14 pg3 pg[3] pcs_d[2] sda_c an[51] 99 00 01 10 11 port g gpio dspi_d peripheral chip select i 2 c_c serial data adc analog input i/o o i/o i v dde3 sha ? ? j14 j14 pg4 pg[4] pcs_d[3] scl_b an[52] 100 00 01 10 11 port g gpio dspi_d peripheral chip select i 2 c_b serial clock adc analog input i/o o i/o i v dde3 sha ? ? k14 k14 pg5 pg[5] pcs_d[4] sda_b an[53] 101 00 01 10 11 port g gpio dspi_d peripheral chip select i 2 c_b serial data adc analog input i/o o i/o i v dde3 sha ? ? l14 l14 pg6 pg[6] pcs_c[1] fec_mdc an[54] 102 00 01 10 11 port g gpio dspi_c peripheral chip select ethernet mgmt. data clock adc analog input i/o o o i v dde3 mha ? ? h15 h15 pg7 pg[7] pcs_c[2] fec_mdio an[55] 103 00 01 10 11 port g gpio dspi_c peripheral chip select ethernet mgmt. data i/o adc analog input i/o o i/o i v dde3 mha ? ? j15 j15 pg8 pg[8] emios[7] fec_tx_clk an[56] 104 00 01 10 11 port g gpio emios channel ethernet transmit clock adc analog input i/o i/o i i v dde3 sha ? ? k15 k15 pg9 pg[9] emios[6] fec_crs an[57] 105 00 01 10 11 port g gpio emios channel ethernet carrier sense adc analog input i/o i/o i i v dde3 sha ? ? l15 l15 pg10 pg[10] emios[5] fec_tx_er an[58] 106 00 01 10 11 port g gpio emios channel ethernet transmit error adc analog input i/o i/o o i v dde3 mha ? ? m15 m15 pg11 pg[11] emios[4] fec_rx_clk an[59] 107 00 01 10 11 port g gpio emios channel ethernet receive clock adc analog input i/o i/o i i v dde3 sha ? ? j16 j16 pg12 pg[12] emios[3] fec_txd[0] an[60] 108 00 01 10 11 port g gpio emios channel ethernet transmit data adc analog input i/o i/o o i v dde3 mha ? ? k16 k16 table 2. mpc5668x signal properties (continued) pin name 1 supported functions 2 gpio (pcr) num 3 pa 4 description i/o type volt- age pad type 5 status package pin locations during reset 6 after reset 7 208 bga 256 bga
pin assignments mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 19 pg13 pg[13] emios[2] fec_txd[1] an[61] 109 00 01 10 11 port g gpio emios channel ethernet transmit data adc analog input i/o i/o o i v dde3 mha ? ? l16 l16 pg14 pg[14] emios[1] fec_txd[2] an[62] 110 00 01 10 11 port g gpio emios channel ethernet transmit data adc analog input i/o i/o o i v dde3 mha ? ? m16 m16 pg15 pg[15] emios[0] fec_txd[3] an[63] 111 00 01 10 11 port g gpio emios channel ethernet transmit data adc analog input i/o i/o o i v dde3 mha ? ? n16 n16 port h (16) ph0 ph[0] emios[31] fec_col 112 00 01 10 11 port h gpio emios channel ethernet collision ? i/o i/o i ? v dde3 sh ? ? t14 t14 ph1 ph[1] emios[30] fec_rx_dv 113 00 01 10 11 port h gpio emios channel ethernet receive data valid ? i/o i/o i ? v dde3 sh ? ? p16 p16 ph2 ph[2] emios[29] fec_tx_en 114 00 01 10 11 port h gpio emios channel ethernet transmit enable ? i/o i/o o ? v dde3 mh ? ? r16 r16 ph3 ph[3] emios[28] fec_rx_er 115 00 01 10 11 port h gpio emios channel ethernet receive error ? i/o i/o i ? v dde3 sh ? ? n15 n15 ph4 ph[4] emios[27] fec_rxd[0] 116 00 01 10 11 port h gpio emios channel ethernet receive data ? i/o i/o i ? v dde3 sh ? ? p15 p15 ph5 ph[5] emios[26] fec_rxd[1] 117 00 01 10 11 port h gpio emios channel ethernet receive data ? i/o i/o i ? v dde3 sh ? ? r14 r14 ph6 ph[6] emios[25] fec_rxd[2] 118 00 01 10 11 port h gpio emios channel ethernet receive data ? i/o i/o i ? v dde3 sh ? ? r15 r15 table 2. mpc5668x signal properties (continued) pin name 1 supported functions 2 gpio (pcr) num 3 pa 4 description i/o type volt- age pad type 5 status package pin locations during reset 6 after reset 7 208 bga 256 bga
mpc5668x microcontrolle r data sheet, rev. 5 pin assignments freescale semiconductor 20 ph7 ph[7] emios[24] fec_rxd[3] 119 00 01 10 11 port h gpio emios channel ethernet receive data ? i/o i/o i ? v dde3 sh ? ? t15 t15 ph8 ph[8] emios[23] 120 00 01 10 11 port h gpio emios channel ? ? i/o i/o ? ? v dde4 sh ? ? p7 p7 ph9 ph[9] emios[22] 121 00 01 10 11 port h gpio emios channel ? ? i/o i/o ? ? v dde4 sh ? ? n8 n8 ph10 ph[10] emios[21] 122 00 01 10 11 port h gpio emios channel ? ? i/o i/o ? ? v dde4 sh ? ? p8 p8 ph11 ph[11] emios[20] 123 00 01 10 11 port h gpio emios channel ? ? i/o i/o ? ? v dde4 sh ? ? n9 n9 ph12 ph[12] emios[19] 124 00 01 10 11 port h gpio emios channel ? ? i/o i/o ? ? v dde4 sh ? ? p9 p9 ph13 ph[13] emios[18] 125 00 01 10 11 port h gpio emios channel ? ? i/o i/o ? ? v dde4 sh ? ? p10 p10 ph14 ph[14] emios[17] 126 00 01 10 11 port h gpio emios channel ? ? i/o i/o ? ? v dde4 sh ? ? p11 p11 ph15 ph[15] emios[16] 127 00 01 10 11 port h gpio emios channel ? ? i/o i/o ? ? v dde4 sh ? ? n11 n11 port j (16) pj0 pj[0] emios[15] pcs_a[4] 128 00 01 10 11 port j gpio emios channel dspi_a peripheral chip select ? i/o i/o o ? v dde4 sh ? ? r7 r7 table 2. mpc5668x signal properties (continued) pin name 1 supported functions 2 gpio (pcr) num 3 pa 4 description i/o type volt- age pad type 5 status package pin locations during reset 6 after reset 7 208 bga 256 bga
pin assignments mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 21 pj1 pj[1] emios[14] pcs_a[5] 129 00 01 10 11 port j gpio emios channel dspi_a peripheral chip select ? i/o i/o o ? v dde4 sh ? ? t7 t7 pj2 pj[2] emios[13] pcs_b[1] 130 00 01 10 11 port j gpio emios channel dspi_b peripheral chip select ? i/o i/o o ? v dde4 sh ? ? r8 r8 pj3 pj[3] emios[12] pcs_b[2] 131 00 01 10 11 port j gpio emios channel dspi_b peripheral chip select ? i/o i/o o ? v dde4 sh ? ? t8 t8 pj4 pj[4] emios[11] pcs_c[3] 132 00 01 10 11 port j gpio emios channel dspi_c peripheral chip select ? i/o i/o o ? v dde4 sh ? ? r9 r9 pj5 pj[5] emios[10] pcs_c[4] 133 00 01 10 11 port j gpio emios channel dspi_c peripheral chip select ? i/o i/o o ? v dde4 sh ? ? t9 t9 pj6 pj[6] emios[09] pcs_d[5] 134 00 01 10 11 port j gpio emios channel dspi_d peripheral chip select ? i/o i/o o ? v dde4 sh ? ? r10 r10 pj7 pj[7] emios[08] pcs_d[1] 135 00 01 10 11 port j gpio emios channel dspi_d peripheral chip select ? i/o i/o o ? v dde4 sh ? ? t10 t10 pj8 pj[8] emios[07] 136 00 01 10 11 port j gpio emios channel ? ? i/o i/o ? ? v dde4 sh ? ? t11 t11 pj9 pj[9] emios[06] 137 00 01 10 11 port j gpio emios channel ? ? i/o i/o ? ? v dde4 sh ? ? r11 r11 pj10 pj[10] emios[05] 138 00 01 10 11 port j gpio emios channel ? ? i/o i/o ? ? v dde4 sh ? ? n12 n12 pj11 pj[11] emios[04] 139 00 01 10 11 port j gpio emios channel ? ? i/o i/o ? ? v dde4 sh ? ? p12 p12 table 2. mpc5668x signal properties (continued) pin name 1 supported functions 2 gpio (pcr) num 3 pa 4 description i/o type volt- age pad type 5 status package pin locations during reset 6 after reset 7 208 bga 256 bga
mpc5668x microcontrolle r data sheet, rev. 5 pin assignments freescale semiconductor 22 pj12 pj[12] emios[03] 140 00 01 10 11 port j gpio emios channel ? ? i/o i/o ? ? v dde4 sh ? ? r12 r12 pj13 pj[13] emios[02] 141 00 01 10 11 port j gpio emios channel ? ? i/o i/o ? ? v dde4 sh ? ? t12 t12 pj14 pj[14] emios[01] 142 00 01 10 11 port j gpio emios channel ? ? i/o i/o ? ? v dde4 sh ? ? r13 r13 pj15 pj[15] emios[00] 143 00 01 10 11 port j gpio emios channel ? ? i/o i/o ? ? v dde4 sh ? ? t13 t13 port k (11) pk0 pk[0] mlbclk sck_b clkout 144 00 01 10 11 port k gpio media local bus clock dspi_b serial clock clkout (test only) i/o i i/o o v ddemlb f? ? l1l1 pk1 pk[1] mlbsig sout_b pcs_d[4] 145 00 01 10 11 port k gpio media local bus signal dspi_b serial data out dspi_d peripheral chip select i/o i/o o o v ddemlb f? ? k1k1 pk2 pk[2] mlbdat sin_b pcs_d[5] 146 00 01 10 11 port k gpio media local bus data dspi_b serial data in dspi_d peripheral chip select i/o i/o i o v ddemlb f? ? k2k2 pk3 pk[3] fr_a_rx ma[0] pcs_c[1] 147 00 01 10 11 port k gpio flexray a receive data adc ext. mux address select dspi_c peripheral chip select i/o i o o v dde2 sh ? ? t3 t3 pk4 pk[4] fr_a_tx ma[1] pcs_c[2] 148 00 01 10 11 port k gpio flexray a transmit data adc ext. mux address select dspi_c peripheral chip select i/o o o o v dde2 mh ? ? r4 r4 pk5 pk[5] fr_a_tx_en ma[2] pcs_c[3] 149 00 01 10 11 port k gpio flexray a transmit enable adc ext. mux address select dspi_c peripheral chip select i/o o o o v dde2 mh ? ? t4 t4 table 2. mpc5668x signal properties (continued) pin name 1 supported functions 2 gpio (pcr) num 3 pa 4 description i/o type volt- age pad type 5 status package pin locations during reset 6 after reset 7 208 bga 256 bga
pin assignments mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 23 pk6 pk[6] fr_b_rx pcs_b[1] pcs_c[4] 150 00 01 10 11 port k gpio flexray b receive data dspi_b peripheral chip select dspi_c peripheral chip select i/o i o o v dde2 sh ? ? r5 r5 pk7 pk[7] fr_b_tx pcs_b[2] pcs_c[5] 151 00 01 10 11 port k gpio flexray b transmit data dspi_b peripheral chip select dspi_c peripheral chip select i/o o o o v dde2 mh ? ? t5 t5 pk8 pk[8] fr_b_tx_en pcs_b[3] pcs_a[1] 152 00 01 10 11 port k gpio flexray b transmit enable dspi_b peripheral chip select dspi_a peripheral chip select i/o o o o v dde2 mh ? ? r6 r6 pk9 pk[9] clkout pcs_d[1] pcs_a[2] bootcfg 153 00 01 10 11 port k gpio clkout (user mode) dspi_d peripheral chip select dspi_a peripheral chip select boot configuration i/o o o o i v dde2 mh boot cfg (pull- down) gpio t6 t6 pk10 pk[10] pcs_b[5] pcs_d[2] pcs_a[3] 154 00 01 10 11 port k gpio dspi_b peripheral chip select dspi_d peripheral chip select dspi_a peripheral chip select i/o o o o v dde2 sh ? ? p6 p6 nexus pins (17) evti evti ? ? nexus event in i v ddenex f? ? ?m11 evto evto ??nexus event out o v ddenex f? ? ?m12 mseo0 mseo[0] ? ? nexus message start/end out o v ddenex f? ? ?m9 mseo1 mseo[1] ? ? nexus message start/end out o v ddenex f? ? ?m8 mcko mcko ? ? nexus message clock out o v ddenex f? ? ?m10 mdo0 mdo[0] ? ? nexus message data out o v ddenex f? ? ?e5 mdo1 mdo[1] ? ? nexus message data out o v ddenex f? ? ?f5 mdo2 mdo[2] ? ? nexus message data out o v ddenex f? ? ?g5 mdo3 mdo[3] ? ? nexus message data out o v ddenex f? ? ?h5 mdo4 mdo[4] ? ? nexus message data out o v ddenex f? ? ?h6 mdo5 mdo[5] ? ? nexus message data out o v ddenex f? ? ?j6 mdo6 mdo[6] ? ? nexus message data out o v ddenex f? ? ?j5 mdo7 mdo[7] ? ? nexus message data out o v ddenex f? ? ?k5 mdo8 mdo[8] ? ? nexus message data out o v ddenex f? ? ?l5 mdo9 mdo[9] ? ? nexus message data out o v ddenex f? ? ?m5 mdo10 mdo[10] ? ? nexus message data out o v ddenex f? ? ?m6 table 2. mpc5668x signal properties (continued) pin name 1 supported functions 2 gpio (pcr) num 3 pa 4 description i/o type volt- age pad type 5 status package pin locations during reset 6 after reset 7 208 bga 256 bga
mpc5668x microcontrolle r data sheet, rev. 5 pin assignments freescale semiconductor 24 mdo11 mdo[11] ? ? nexus message data out o v ddenex f? ? ?m7 miscellaneous pins (9) extal extal extclk ? ? main crystal oscillator input external clock input i i v ddsyn a extal a14 a14 xtal xtal ? ? main crystal oscillator output o v ddsyn axtala13a13 tdi tdi ? ? jtag test data input i v dde2 sh tdi (pull up) j3 j3 tdo tdo ? ? jtag test data output o v dde2 mh tdo (pull up 8 )m3 m3 tms tms ? ? jtag test mode select input i v dde2 mh tms (pull up) l3 l3 tck tck ? ? jtag test clock input i v dde2 sh tck (pull down) p3 p3 jcomp jcomp ? ? jtag compliancy i v dde2 sh jcomp (pull down) k3 k3 test test ? ? test mode select i v dde3 ih test 9 m13 m13 reset reset ? ? external reset i/o v dde1 mh reset (pull up) a11 a11 1 the primary signal name is used as the pin labe l on the bga map for identification purposes. 2 each line in the signal name column corresponds to a separate signal function on the pin. for all device i/o pins, the primary, alternate, or gpio signal functions are designated in the pa fi eld of the system integration unit (siu) pcr registers except where explicitly noted. 3 the gpio number is the same as the corre sponding pad configuration register (siu_pcr n ) number. 4 the pa bitfield in the siu_pcr n register selects the signal function for the pin. a dash in the description field of this table indicates that this value for pc is reserved on this pin, and should not be used. 5 the pad type is indicated by one or more of the following abbr eviations: a?analog, f?fast speed, h?high voltage, i?input-only, m?medium speed, s?slow speed. for example, pad type sh designates a slow high-voltage pad. 6 the status during reset pin is sampled after the internal po r is negated. prior to exitin g por, the signal has a high impedance. the terminology used in this column is: o ? output, i ? input, up ? weak pull up enabled, down ? weak pulldown enabled, low ? output driven low, high ? output driven high. a dash on the left side of the slash denotes that both the input a nd output buffers for the pin are off. a dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin. the signal name to the left or right of the slash indicates the pin is enabled. 7 the function after reset of a gpi function is general purpose input. a dash on the left side of the slash d enotes that both the input and output buffers for the pin are off. a dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin. 8 pullup is enabled only when jcomp is negated. 9 tie to v ss for normal operation. table 2. mpc5668x signal properties (continued) pin name 1 supported functions 2 gpio (pcr) num 3 pa 4 description i/o type volt- age pad type 5 status package pin locations during reset 6 after reset 7 208 bga 256 bga
pin assignments mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 25 3.3.1 power and ground supply summary table 3. mpc5668x power/ground pin name function description voltage 1 1 nominal voltages. package pin locations 208 256 v dd internal logic power 1.2 v d4, d10, h4, g1 3, k13, n5 d4, d10, h4, g13, k13, n5 v dde1 external i/o power 3.3?5.0 v d6 d6 v dde2 l4 l4 v dde3 j13 j13 v dde4 n10 n10 v dda analog power 3.3?5.0 v b15 b15 v dd33 3.3 v i/o power 3.3 v l13 l13 v ddemlb media local bus power 2.5 or 3.3 v k4 k4 v ddenex 2 2 dedicated nexus power pin on 256-pin package only. on the 208-pin package, vddenex is tied to vss internal to the package substrate and is not available externally. nexus power 3.3 v ? e6, k11, l7 v rcsel voltage regulator select v ssa / v dda h13 h13 v rc voltage regulator control voltage 3.3?5.0 v b10 b10 v rcctl voltage regulator control output ? 3 3 base current to external npn power transistor. voltage may vary. b11 b11 v ddsyn clock synthesizer power 3.3 v a12 a12 v rh analog high voltage reference 3.3? 5.0 v b16 b16 v rl analog low voltage reference 0 v c16 c16 v ss ground 0 v a1, a16, d7, g4, g[7:10], h[7:10], j[7:10], k[7:10], n13, t1, t16 a1, a16, d7, e[7:12], f[7:12], g4, g[6:12], h[7:12], j[7:12], k[6:10], k12, l[8:10], l12, n13, t1, t16 v ssa analog ground 0 v c15 c15 v sssyn clock synthesizer ground 0 v a15 a15
mpc5668x microcontrolle r data sheet, rev. 5 electrical characteristics freescale semiconductor 26 4 electrical characteristics this section contains detailed information on power cons iderations, dc/ac electrical ch aracteristics, and ac timing specifications for the mpc5668x. 4.1 maximum ratings table 4. absolute maximum ratings 1 1 functional operating conditions are given in the dc electrical specifications. absolute maximum ratings are stress ratings only , and functional operation at the maxima is not guaranteed. stress beyond the listed maxima may affect device reliability or caus e permanent damage to the device. spec characteristic symbol min max unit 1 1.2 v core supply voltage v dd ?0.3 1.32 2 2 2.0 v for 10 hours cumulative time, 1.2 v +10% for time remaining. v 2 3.3 v clock synthesizer voltage v ddsyn ?0.3 3.6 v 3 3.3 v i/o buffer voltage v dd33 ?0.3 3.6 v 4 3.3?5.0 v voltage regulator control voltage 3 3 vrc cannnot be 100mv higher than vdda. vddsyn and vdd33 cannot be 100mv higher than vrc. v rc ?0.3 5.5 v 5 3.3?5.0 v analog supply voltage (reference to v ssa )v dda ?0.3 5.5 v 6 3.3?5.0 v external i/o supply voltage 4 4 all functional non-supply i/o pins are clamped to v ss and v dde x . v dde1 5 v dde2 5 v dde3 5 v dde4 5 5 v dde x are separate power segments and may be powered independen tly with no differential volt age constraints between the power segments. ?0.3 ?0.3 ?0.3 ?0.3 5.5 5.5 5.5 5.5 v 7 2.5?3.3 v external i/o supply voltage (mlb) v ddemlb 5 ?0.3 3.6 v 8 3.3 v external i/o supply voltage (nexus) v ddenex 5 ?0.3 3.6 v 9 dc input voltage 6 v dde1 , v dde2 , v dde3 , v dde4 v ddemlb , v ddenex v in ?1.0 7 ?1.0 6 v dde x + 0.3 v 8 v dde x + 0.3 v 7 v 10 analog reference high voltage v rh ?0.3 minimum of 5.5 or v dda +0.3 v 11 analog reference low voltage v rl ?0.3 5.5 v 12 v ss to v ssa differential voltage v ss ?v ssa ?100 100 mv 13 v ss to v sssyn differential voltage v ss ?v sssyn ?100 100 mv 14 maximum dc digital input current 9 (per pin, applies to all digital f, mh, sh, and ih pins) i maxd ?2 2 ma 15 maximum dc analog input current 10 (per pin, applies to all analog ae and a pins) i maxa ?3 3 ma 16 storage temperature range t stg ?55.0 150.0 o c 17 maximum solder temperature 11 t sdr ? 235.0 o c 18 moisture sens itivity level 12 msl ? 3
electrical characteristics mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 27 4.2 thermal characteristics 4.2.1 general notes for specifications at maximum junction temperature an estimation of the chip junction temperature, t j , can be obtained from the equation: t j =t a +(r ? ja ? p d ) eqn. 1 where: 6 ac signal over and undershoot of the input voltages of up to 2.0 v is permitted for a cumulative duration of 60 hours over the complete lifetime of the device (injection current does not need to be limited for this duration). 7 internal structures will hold the in put voltage above ?1.0 v if the inje ction current limit of 2 ma is met. 8 internal structures hold the input voltage below this maximum voltage on all pads powered by v dde supplies, if the maximum injection current specification is met (25 ma for all pins) and v dde is within operating voltage specifications. 9 total injection current for all pins (including both digital and analog) must not exceed 25 ma. 10 total injection current for all analog input pins must not exceed 15 ma. 11 solder profile per cdf-aec-q100. 12 moisture sensitivity per jedec test method a112. table 5. thermal characteristics spec characteristic symbol unit value 208 mapbga 256 mapbga 1 junction to ambient 1, 2 natural convection (single layer board) 1 junction temperature is a function of on-chip power dissi pation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipa tion of other components on the board, and board thermal resistance. 2 per semi g38-87 and jedec jesd51-2 with the single layer board horizontal. r ? ja c/w 39 39 2 junction to ambient 1, 3 natural convection (four layer board 2s2p) 3 per jedec jesd51-6 with the board horizontal. r ? ja c/w 24 24 3 junction to ambient 1, 3 (@200 ft./min., single layer board) r ? jma c/w 31 31 4 junction to ambient 1, 3 (@200 ft./min., four layer board 2s2p) r ? jma c/w 20 20 5 junction to board 4 4 thermal resistance between the die and the printed circuit b oard per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. r ? jb c/w 13 13 6 junction to case 5 5 indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plate temperature used for the case temperature. r ? jc c/w 6 6 7 junction to package top 6 natural convection 6 thermal characterization parameter indica ting the temperature difference between package top and the junction temperature per jedec jesd51-2. ? jt c/w 2 2
mpc5668x microcontrolle r data sheet, rev. 5 electrical characteristics freescale semiconductor 28 t a = ambient temperatur e for the package ( o c) r ? ja = junction to ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) the supplied thermal resistances are provided based on jedec jesd51 series of stan dards to provide consistent values for estimations and comparisons. the difference be tween the values determined on the single-l ayer (1s) board and on the four-layer board with two signal layers and a power and a ground plane (2s 2p) clearly demonstrate that th e effective thermal resistance of the component is not a constant. it depends on the construction of the application board (number of planes), the effective size of the board which cools the component, ho w well the component is thermally and elect rically connected to the planes, and the power being dissipated by adjacent components. connect all the ground and power balls to the respective planes with one via per ball. using fewer vias to connect the package to the planes reduces the thermal perfor mance. thinner planes also reduce the thermal performance. when the clearance between through vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. as a general rule, the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. the value obtained on the board with the internal planes is usually appropriate if the application board has one oz. (35 micron nominal thickness) internal planes, the components are well separated, and the overall power dissipation on the board is less than 0.02 w/cm 2 . the thermal performance of any component depends strongly on th e power dissipation of surrounding components. in addition, the ambient temperature varies widely wi thin the application. for many natura l convection and especially closed box applications, the board temperature at the perimeter (edge) of th e package is approximately the sa me as the local air temperatu re near the device. specifying the local ambient conditions explicitly as the board temperature provides a more precise descriptio n of the local ambient condi tions that determine the temperature of the device. at a known board temperature, the junction temperature is estimated using the following equation: t j =t b +(r ? jb ? p d ) eqn. 2 where: t j = junction temperature ( o c) t b = board temperature at the package perimeter ( o c/w) r ? jb = junction to board thermal resistance ( o c/w) per jesd51-8 p d = power dissipation in the package (w) when the heat loss from the package case to the air can be i gnored, acceptable predictions of j unction temperature can be made. the application board should be similar to the thermal test condition, with the component soldered to a board with internal planes. historically, the thermal resistance has frequently been expres sed as the sum of a junction to case thermal resistance and a ca se to ambient thermal resistance: r ? ja =r ? jc +r ? ca eqn. 3 where: r ? ja = junction to ambient thermal resistance ( o c/w) r ? jc = junction to case thermal resistance ( o c/w) r ? ca = case to ambient thermal resistance ( o c/w) r ? jc is device related and cannot be influenced by the user. the user controls the thermal envi ronment to change the case to ambient thermal resistance, r ? ca . for instance, the user can chan ge the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the ther mal dissipation on the printed circuit board surrounding the
electrical characteristics mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 29 device. this description is most useful for packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. for most pa ckages, a better model is required. a more accurate two-resistor thermal model can be constructed from the junction to board ther mal resistance and the junction to case thermal resistance. the junction to cas e covers the situation where a heat sink will be used or where a substantial amo unt of heat is dissipated from the top of th e package. the junction to board thermal resistance describes the thermal performance when most of the heat is conducted to th e printed circuit board. this model can be used for either hand estimations or for a computational fluid dynamics (cfd) thermal model. to determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter ( ? jt ) can be used to determine the junction temperat ure with a measurement of the temperature at the top center of the package case using the following equation: t j =t t +( ? jt ? p d ) eqn. 4 where: t t = thermocouple temperature on top of the package ( o c) ? jt = thermal characterization parameter ( o c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured per jesd51-2 specification using a 40-gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple juncti on and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to av oid measurement errors caused by cooling effects of the thermocouple wire. references: semiconductor equipment and materials international 3081 zanker road san jose, ca 95134 (408) 943-6900 mil-spec and eia/jesd (jedec) specifi cations are available from global engi neering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org . 1. c.e. triplett and b. joiner, ?an experimental characterization of a 272 pbga within an automotive engine controller module,? proceedings of semi therm, san diego, 1998, pp. 47?54. 2. g. kromann, s. shidore, and s. addison, ?thermal mo deling of a pbga for air-cooled applications,? electronic packaging and production, pp. 53?58, march 1998. 3. b. joiner and v. adams, ?measurement and simulation of junction to board thermal resistance and its application in thermal modeling,? proceedings of se mitherm, san diego, 1999, pp. 212?220.
mpc5668x microcontrolle r data sheet, rev. 5 electrical characteristics freescale semiconductor 30 4.3 esd characteristics 4.4 vrc electrical specifications 4.5 dc electrical specifications table 6. esd ratings 1, 2 1 all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. 2 a device will be defined as a failure if after exposure to esd pulses the device no longer m eets the device specification requirements. complete dc parametric and f unctional testing shall be performed per a pplicable device specification at room temperature followed by hot temperature, unless s pecified otherwise in the device specification. characteristic symbol value unit esd for human body model (hbm) 2000 v hbm circuit description r1 1500 ohm c100 pf esd for field induced charge model (fdcm) 750 (corner pins) v 250 (all other pins) number of pulses per pin: positive pulses (hbm) negative pulses (hbm) ? ? 1 1 ? ? interval of pulses ? 1 second table 7. vrc electrical specifications spec characteristic symbol min max units 1 current which can be sourced by v rcctl i_v rcctl 6.25 a 20 ma ? 2 minimum required gain from external circuit: i dd / i_v rcctl (@v dd =1.32v) 1 ?40 ? c 25 ? c 150 ? c 1 assumes ?typical usage? currents which will vary with application. beta 50 50 50 500 table 8. dc electrical specifications spec characteristic symbol min max unit 1 maximum operating temperature range ? die junction temperature t j ?40.0 150.0 o c 2 3.3 v clock synthesizer voltage 1 v ddsyn 3.0 3.6 2, 3 v 3 3.3 v i/o buffer voltage 1 v dd33 3.0 3.6 2, 3 v 4 3.3?5.0 v voltage regulator reference voltage 1 v rcsel =v ssa v rcsel =v dda v vrc 3.0 4.5 3.6 5.5 v 5 3.3?5.0 v analog supply voltage v dda maximum of 3.0 v or v vrc ?0.1 5.5 2, 4 v
electrical characteristics mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 31 6 3.3?5.0 v external i/o supply voltage 5 v dde1 v dde2 2 v dde3 2 v dde4 2 3.0 3.0 3.0 3.0 5.5 2, 5 5.5 2,5 5.5 2, 5 5.5 2, 5 v 7 2.5 v ? 3.3 v external i/o supply voltage (mlb) v ddemlb 2, 6 2.375 3.6 1, 2 v 8 3.3 v external i/o supply voltage (nexus) v ddenex 2 3.0 3.6 1, 2 v 9 pad input high voltage hysteresis enabled hysteresis disabled (iha/sh/sha/mh/mha) 7, 8 hysteresis disabled (f) v ih 0.65 ? v dde 0.55 ? v dde 0.55 ? v dde v dde +0.3 v 10 pad input low voltage hysteresis enabled hysteresis disabled (iha/sh/sha/mh/mha) 7, 8 hysteresis disabled (f) v il v ss ?0.3 0.35 ? v dde 0.40 ? v dde 0.40 ? v dde v 11 pad input hysteresis v hys 0.1 ? v dde v 12 analog (iha) input voltage v indc v ssa ?0.3 v dda +0.3 v 13 pad output high voltage 9, 10, 11 v oh 0.8 ? v dde ?v 14 pad output low voltage 1, 11 v ol ?0.2 ? v dde v 15 input capacitance (digital pins: pad type f, mh, sh) 7 c in ?7pf 16 input capacitance (analog pins: pad type iha) 7, 8 c in_a ?10pf 17 input capacitance (shared digital/analog pins: mha, sha) 7 c in_m ?12pf 18 i/o weak pull up/down absolute current 7, 12 pad f: 2.375 v ? 3.6 v pad sh/mh/iha: 3.0 v ? 3.6 v pad sh/mh/iha: 4.5 v ? 5.5 v i act 25 10 35 180 95 200 ? a 19 i/o input leakage current 13 i inact_d ?2.5 2.5 ? a 20 dc injection current (per pin) i ic ?1.0 1.0 ma 21 analog input current, channel off 14 (analog pins iha) 7, 8 i inact_a ?150 150 na 22 analog reference high voltage v rh v dda ?500 v dda mv 23 analog reference low voltage v rl v ssa v ssa +500 mv 24 v ss to v ssa differential voltage v ss ?v ssa ?100 100 mv 25 v sssyn to v ss differential voltage v sssyn ?v ss ?100 100 mv 26 slew rate on v dda , v dde x , v ddsyn , v dd33 , and v rc power supply pins v ramp ?100v/ms 27 capacitive supply load (v dd )v load 8?f 28 capacitive supply load (v dd33 , v ddsyn )v load 1?f 1 when v rcsel = v ssa (low), v ddsyn and v dd33 are externally supplied. when v rcsel = v dda (high), v ddsyn and v dd33 are generated by internal voltage regulators. when v rcsel = v ssa (low), v ddsyn and v dd33 cannot be 100 mv higher than v rc . table 8. dc electrical specifications spec characteristic symbol min max unit
mpc5668x microcontrolle r data sheet, rev. 5 electrical characteristics freescale semiconductor 32 4.6 operating current sp ecifications 2 voltage overshoots during a high-to-low or low-to-hi gh transition must not exceed 10 seconds per instance. 3 5.3 v for 10 hours cumulative time, 3.3 v +10% for time remaining. 4 6.4 v for 10 hours cumulative time, 5.0 v +10% for time remaining. 5 v dde1 ? v dde4 are separate power segments and may be powered independently with no differential voltage constraints between the power segments. v dde1 ? v dde3 pad power segments contain adc analog input channels and thus the input analog signal level may be clamped to the v dde level, resulting in inaccurate adc results if the v dde voltage level is less than v dda . 6 when v rcsel = v dda (high), the internally generated v dd33 voltage may be used to power v ddemlb as long as the pk[0:2] pads remain in the disabled default state with their output buffers, input buffers, and pull devices disabled. 7 the pad type is indicated by one or more of the following abbr eviations: a?analog, f?fast speed, h?high voltage, i?input-only, m?medium speed, s?slow speed. for example, pa d type sh designates a slow high-voltage pad. 8 the iha pads are related to v dda . 9 characterization based capability: ioh_f = {12, 20, 30, 40} ma and iol_f = {24, 40, 50, 65} ma for {00, 01,10, 11} drive mode with v dde = 3.0 v; ioh_f = {7, 13, 18, 25} ma and iol_f = {18, 30, 35, 50} ma for {00, 01, 10, 11} drive mode with v dde =2.25 v; ioh_f = {3, 7, 10, 15} ma and iol_f = {12, 20, 27, 35} ma for {00, 01, 10, 11} drive mode with v dde =1.62 v. 10 characterization based capability: ioh_s = {6, 11.6} ma and iol_s = {9.2, 17.7} ma for {slow, medium} i/o with v ddeh = 4.5 v; ioh_s = {2.8, 5.4} ma and iol_s = {4.2, 8. 1} ma for {slow, medium} i/o with v ddeh = 3.0 v 11 all v ol /v oh values 100% tested with 2 ma load. 12 absolute value of current, measured at v il and v ih . 13 weak pull up/down inactive. measured at v dde = 5.25 v. applies to pad types: sh and mh. leakage specification guaranteed only when power supplies are within specified operating conditions. 14 maximum leakage occurs at maximum operating temperature. l eakage current decreases by approximately one-half for each 8 to 12 o c, in the ambient temperature range of 50 to 125 o c. applies to pad types: pad_a and pad_ae. table 9. operating currents spec characteristic symbol typ 1 25 ? c ambient max 1 ?40?150 ? c junction unit equations i total =i dde +i dda +i rh +i dd33 +i ddsyn +i rc +i dd i dde =i dde1 +i dde2 +i dde3 +i dde4 +i ddemlb ? ? ? ? 1v dde current v dde(1,2,3,4) @ 3.0v?5.5v v ddemlb @ 2.375v?3.6v static 2 dynamic 3 i dde 0 note 3 30 25 ? a ma 2v dda current v dda @ 3.0v?5.5v run mode sleep mode ? optional 32 khz osc enabled i dda 1 20 +5 30 50 +15 ma ? a ? a 3v rh current v rh @ 3.0v?5.5v run mode sleep mode i rh 300 1 700 30 ? a ? a
electrical characteristics mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 33 4v dd33 current v dd33 @ 3.0v?3.6v run mode sleep mode i dd33 10 10 20 20 ma ? a 5v ddsyn current v dd33 @ 3.0v?3.6v run mode sleep mode ? optional 4 4?40 mhz osc enabled w/ no clock ? optional 4 4?40 mhz osc enabled w/ clock i ddsyn 5 1 +150 +300 10 20 +350 +400 ma ? a ? a ? a 6v rc current (excluding i dd , i dd33 , i ddsyn ) 5 v rc @ 3.135 v ? 5.5 v run mode sleep mode ? optional 4 16mirc enabled i rc 1 0 +40 10 10 +60 ma ? a ? a 7v dd current v dd @ 1.08 v ? 1.32 v run mode (maximum @ 116 mhz) 6 sleep mode ? optional 4 128kirc enabled ? optional 4 16mirc enabled ? optional 4 32 khz osc enabled ? optional 4 4?40 mhz osc enabled w/ no clock ? optional 4 4?40 mhz osc enabled w/ clock ? optional 4 32 kb ram ? optional 4 64 kb ram ? optional 4 128 kb ram i dd 200 100 +5 +200 +5 +5 +150 +10 +20 +40 340 900 +10 +220 +20 +20 +200 +150 +300 +600 ma ? a ? a ? a ? a ? a ? a ? a ? a ? a 1 typ ? nominal voltage levels and functional activity. max ? maximum voltage levels and functional activity. 2 static state of pins is when input pins are disabled or not bei ng toggled and driven to a valid input level, output pins are no t toggling or driving against any current loads, and internal pull devices are disabled or not pulling against any current loads. 3 dynamic current from pins is application-sp ecific and depends on active pull devices, switching outputs, output capacitive and current loads, and switching inputs. refer to ta b l e 1 0 for more information. 4 optional currents are values that should be added to their respecti ve current specifications to obtain the actual value for tha t specification when the optional function is active. the plus sign (+) in the typ and max columns indicates these optional currents. for example, v ddsyn in sleep mode draws 1 . ? a (typ). with the optional 4?40 mhz osc enabled w/ no clock, add 150 . ? a for a total of 151 . ? a (typ). 5 v rc current excluding the current supply to v dd33 , v ddsyn and v dd from v rc . 6 maximum supply current transition: 50ma per 20 ? s observation window. table 9. operating currents (continued) spec characteristic symbol typ 1 25 ? c ambient max 1 ?40?150 ? c junction unit
mpc5668x microcontrolle r data sheet, rev. 5 electrical characteristics freescale semiconductor 34 4.7 i/o pad current specifications the power consumption of an i/o segment depends on the usage of the pins on a particular segment. the power consumption is the sum of all output pin currents for a particular segment. the output pin curr ent can be calculated from table 10 based on the voltage, frequency, and load on the pin. use linear scaling to calculate pin cu rrents for voltage, frequency, and load parameters that fall outside the values given in table 10 . table 10. i/o pad average i dde specifications 1 1 these are typical values that are esti mated from simulation and not tested. currents apply to output pins only. spec pad type 2 2 slow = sh or sha; medium = mh or mha; fast = f; input = iha. see ta b l e 2 . symbol period (ns) load 3 (pf) 3 all loads are lumped. v dde (v) drive/slew rate select i dde avg (ma) i dde rms (ma) 1 slow i drv_ssr_hv 37 50 5.5 11 14 2 130 50 5.5 01 5.3 3 650 50 5.5 00 1.1 4 840 200 5.5 00 3 6 medium i drv_msr_hv 24 50 5.5 11 9 7 62 50 5.5 01 2.5 8 317 50 5.5 00 0.5 9 425 200 5.5 00 1.5 11 fast i drv_fc 10 50 3.6 11 50.4 101.6 12 10 30 3.6 10 14.2 57.3 13 10 20 3.6 01 16.4 43.6 14 10 10 3.6 00 9.8 15.9 15 10 50 2.75 11 22.9 45.3 16 10 30 2.75 10 6.7 25.3 17 10 20 2.75 01 4.5 17.3 18 10 10 2.75 00 3 9.6 19 input i drv_i_hv 7 0.5 5.5 n/a n/a n/a
electrical characteristics mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 35 4.7.1 i/o pad v dd33 current specifications the power consumption of the v dd33 supply is dependent on the usage of the pins on all i/o segments. the power consumption is the sum of all input and output pin v dd33 currents for all i/o segments. the output pin v dd33 current can be calculated from table 11 based on the voltage, frequency, and load on all pad f pins. the input pin v dd33 current can be calculated from table 11 based on the voltage, frequency, and load on all pad mh pins. use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in table 11 . table 11. i/o pad average i dd33 specifications 1 1 these are typical values that are estimated from simu lation and not tested. currents apply to output pins only. spec pad type 2 2 slow = sh or sha; medium = mh or mha; fast = f; input = iha. see ta bl e 2 . symbol period (ns) load 3 (pf) 3 all loads are lumped. drive select i dd33 avg (a) i dd33 rms (a) 1 slow i drv_ssr_hv 100 50 11 0.8 235.7 2 200 50 01 0.04 87.4 3 800 50 00 0.06 47.4 4 800 200 00 0.009 47 5 medium i drv_msr_hv 40 50 11 6 100 50 01 0.11 76.5 7 500 50 00 0.02 56.2 8 500 200 00 0.01 56.2 9 input i drv_i_hv 70.5n/a table 12. i dd33 pad average dc current 1 1 these are typical values that are esti mated from simulation and not tested . currents apply to output pins only. spec pad type 2 2 slow = sh or sha; medium = mh or mha; fast = f; input = iha. see ta bl e 2 . symbol period (ns) load 3 (pf) 3 all loads are lumped. v dd33 (v) v dde (v) drive select i dd33 avg (a) i dd33 rms (a) 1 fast i drv_fc 10 50 3.6 3.6 11 3.32 11.77 2 10 30 3.6 3.6 10 2.28 7.07 3 10 20 3.6 3.6 01 1.73 5.75 4 10 10 3.6 3.6 00 1.39 4.77 5 10 50 3.6 2.75 11 2.3 7.81 6 10 30 3.6 2.75 10 1.64 4.96 7 10 20 3.6 2.75 01 1.37 4.31 8 10 10 3.6 2.75 00 1.06 4.09
mpc5668x microcontrolle r data sheet, rev. 5 electrical characteristics freescale semiconductor 36 4.8 low voltage characteristics 4.9 oscillators electrical characteristics table 13. low voltage monitors spec characteristic symbol min typical max unit 1 power-on-reset assert level 1 1 monitors v dda. v por 1.5 ? 2.8 v 2 low voltage monitor 3.3 v 2 assert level de-assert level 2 monitors v dd33. v lvi 3 3 a v lvi33d 3.00 3.04 3.05 3.12 3.10 3.19 v 3 low voltage monitor synthesizer 3 assert level de-assert level 3 monitors v ddsyn. v lvisyna v lvisynd 3.00 3.04 3.05 3.12 3.10 3.19 v 4 low voltage monitor 3.0 v low threshold 1 vrcsel = v ssa assert level de-assert level vrcsel =v dda assert level de-assert level v lv i _ v d da _ l oa v lvi_vdda_lod v lv i _ v d da _ l oa v lvi_vdda_lod 3.00 3.04 3.25 3.35 3.05 3.12 3.35 3.45 3.10 3.19 3.48 3.55 v 5 low voltage monitor 5.0 v 1, 4 assert level de-assert level 4 disabled when v rcsel =v ssa . v lvi _ v d da _ a v lv i _ v d da _ d 4.35 4.45 4.475 4.575 4.55 4.65 v 6 low voltage monitor 5.0 v high threshold 1, 5 assert level de-assert level v lv i _ v d da _ h a v lv i _ v d da _ h d 4.50 4.50 4.675 4.675 4.80 4.80 v table 14. 3.3 v high frequency external oscillator spec characteristic symbol min max unit 1 frequency range f ref 4 1 40 mhz 2 duty cycle of reference t dc 40 60 % 3 extal input high voltage external crystal mode 2 external clock mode v ihext v xtal +0.4 0.65 ? v ddsyn v ddsyn +0.3 v ddsyn +0.3 v 4 extal input low voltage external crystal mode 3 external clock mode v ilext v ddsyn ?0.3 v ddsyn ?0.3 v xtal ?0.4 0.35 ? v ddsyn v 5 xtal current 4 i xtal 13ma 6 total on-chip stray capacitance on xtal c s_xtal ?3pf 7 total on-chip stray capacitance on extal c s_extal ?3pf
electrical characteristics mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 37 8 crystal manufacturer?s recommended capacitive load c l see crystal specification see crystal specification pf 9 discrete load capacitance to be connected to extal c l_extal ?2 ? c l ?c s_extal ? c pcb_extal 5 pf 10 discrete load capacitance to be connected to xtal c l_xtal ?2 ? c l ?c s_xtal ?c pcb_xtal 5 pf 11 startup time t startup ?10ms 1 when pll frequency modulation is active, reference frequencie s less than 8 mhz will distort the modulated waveform and the effects of this on emissions is not characterized. 2 this parameter is meant for those who do not use quartz crys tals or resonators, but instead use can oscillators in crystal mode. in that case, v extal ?v xtal ? 400 mv criteria has to be met for oscillator?s comparator to produce output clock. 3 this parameter is meant for those who do not use quartz crys tals or resonators, but instead use can oscillators in crystal mode. in that case, v xtal ?v extal ? 400 mv criteria has to be met for oscillator?s comparator to produce output clock. 4 i xtal is the oscillator bias current out of the xtal pin with both extal and xtal pins grounded. 5 c pcb_extal and c pcb_xtal are the measured pcb stray capacitan ces on extal and xtal, respectively. table 15. 5 v low frequency (32 khz) external oscillator spec characteristic symbol min. max unit 1 frequency range f ref32 32 40 khz 2 duty cycle of reference t dc32 40 60 % 3 xtal32 current 1 1 i xtal32 is the oscillator bias current out of the xtal 32 pin with both extal32 and xtal32 pins grounded. i xtal32 ?3 ? a 4 crystal manufacturer?s recommended capacitive load c l32 see crystal specification see crystal specification pf 5 startup time t startup ?2s table 16. 5 v high frequency (16 mhz) internal rc oscillator spec characteristic symbol range min typ max unit 1 frequency before trim 1 1 across process, voltage, and temperature. f ut 35% 10.4 16 21.6 mhz 2 frequency after loading factory trim 2 2 across voltage and temperature. f t 7% 14.9 16 17.1 mhz 3 application trim resolution 3 3 fixed voltage and temperature. t s ?? ? ? 0 ? 5% 4 application frequency trim step 3 f s ? ? 300 ? khz 5 startup time t startup ? ? ? 500 ns table 14. 3.3 v high frequency external oscillator (continued) spec characteristic symbol min max unit
mpc5668x microcontrolle r data sheet, rev. 5 electrical characteristics freescale semiconductor 38 4.10 fmpll electrical characteristics table 17. 5v low frequency (128 khz) internal rc oscillator spec characteristic symbol range min typ max unit 1 frequency before trim 1 1 across process, voltage, and temperature. f ut128 35% 83.2 128 172.8 khz 2 frequency after loading factory trim 2 2 across voltage and temperature. f t128 7% 119.0 128 137.0 khz 3 application trim resolution 3 3 fixed voltage and temperature. t s128 ?? ? ? 2% 4 application frequency trim step 3 f s128 ? ? 4 ? khz 5 startup time s t128 ?? ? 100 ? s table 18. fmpll electrical specifications 1 1 v ddsyn = 3.0 v to 3.6 v, v ss =v sssyn =0v, t a =t l to t h . spec characteristic symbol min max unit 1 system frequency 2 f sys ? 116 mhz 2 pll reference frequency range f ref 440mhz 3 pll frequency f pll mhz 4 loss of reference frequency 3 f lor 100 2000 khz 5 self clocked mode frequency f scm 16 64 mhz 6 pll lock time 4 t lpll ? 400 ? s 7 duty cycle of reference t dc 40 60 % 8 frequency un-lock range f ul ?4.0 4.0 % f sys 9 frequency lock range f lck ?2.0 2.0 % f sys 10 clkout period jitter, 5 measured at f sys max cycle-to-cycle jitter c jitter ?5 5 % f sys 11 clkout jitter at ? 50 s period c jitter ?250 250 ns 12 peak-to-peak frequency modulation range limit 6,7 (f sys max must not be exceeded) c mod 04 %f sys 13 fm depth tolerance 8 c mod_err ?0.50 0.50 %f sys 14 vco frequency 9 f vco 192 600 mhz 15 modulation rate limits 10 f mod 0.400 1 mhz f vco min ?? erfd 1 + ?? ------------------------------
electrical characteristics mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 39 4.11 adc electrical characteristics 4.12 flash memory electrical characteristics 2 the maximum frequency value is with frequency modulation disa bled. if frequency modulation is enabled, the maximuum frequency value should be de-rated by the percentage of modula tion enabled so that the maximum frequency is not exceeded. 3 ?loss of reference frequency? is the reference frequency detected internally, which transitions the pll into self clocked mode. 4 this specification applies to the period r equired for the pll to re-lock after changing the mfd frequency control bits in the synthesizer control register (syncr). from power up with crystal oscillator reference, lock time will be additive with crystal startup time. 5 values are with frequency modulation disabled. if frequen cy modulation is enabled, jitter is the sum of c jitter +c mod . 6 modulation depth selected must not result in f pll value greater than the f pll maximum specified value. 7 maximum and minimum variations from programmed modulati on depth are 2%, 3%, and 4% peak-to-peak. use only these settings. 8 depth tolerance is the programmed modulation depth 0.25% of f sys . 9 see the block guide for vco frequency synthesis equations. 10 modulation rates less than 400 khz will result in exceedingly long fm calibration durations. modulation rates greater than 1 mhz will result in reduced calibration accuracy. table 19. adc conversion specifications (operating) spec characteristic symbol min max unit 1 analog high reference voltage v rh v dda ?0.5 v dda v 2 analog low reference voltage v rl 00.5v 3 analog input voltage av in v rl v rh v 4 sampling frequency f s ?1.53mhz 5 maximum adc clock frequency f max ?60mhz 6 sampling time v dda =3.0v?3.6v v dda >3.6v?5.5v t s 250 125 ?ns 7 differential non linearity dnl ?1.0 1.0 lsb 8 integral non linearity inl ?1.5 1.5 lsb 9 offset error ofs ?1.0 1.0 lsb 10 gain error gne ?2.0 2.0 lsb 11 total unadjusted error 1 1 tue assumes no pin activity on pins adjacent to analog channel or output driver activity on corresponding v dde segment. tue ?2.0 2.0 lsb table 20. flash program and erase specifications 1 spec characteristic symbol min initial max 2 max 3 unit 1 double word (64 bits) program time 4 t dwprogram ?? 500 ? s 2 page (128 bits and 256 bits) program time 4 t pprogram ? 160 500 ? s 3 16 kb block pre-program and erase time t 16kpperase ? 1000 5000 ms 4 64 kb block pre-program and erase time t 64kpperase ? 1800 5000 ms 5 128 kb block pre-program and erase time t 128kpperase ? 2600 7500 ms
mpc5668x microcontrolle r data sheet, rev. 5 electrical characteristics freescale semiconductor 40 4.13 pad ac specifications 6 256 kb block pre-program and erase time t 256kpperase ? 5200 15,000 ms 7 wait states relative to system frequency 5 pfcrp n [rwsc] = pfcrp n [apc] = 0b000; pfcrp n [wwsc] = 0b01 pfcrp n [rwsc] = pfcrp n [apc] = 0b001; pfcrp n [wwsc] = 0b01 pfcrp n [rwsc] = pfcrp n [apc] = 0b010; pfcrp n [wwsc] = 0b01 pfcrp n [rwsc] = pfcrp n [apc] = 0b011 ? 0b111; pfcrp n [wwsc] = 0b01 t rwsc ? ? ? ? ? ? ? ? 30 60 90 f sys max mhz 8 recovery time t recover ?? 45 ? s 1 typical program and erase times assume nominal supply values and operation at 25 o c. 2 initial factory condition: ? 100 ? program/erase cycles, nominal suppl y values and o peration at 25 o c. 3 the maximum time is at worst case cond itions after the spec ified number of program/erase cycles. this maximum value is characterized but not guaranteed. 4 actual hardware programming time. this does not include software overhead. 5 wait state timing is based on the system clock frequency and thus is same for all masters. table 21. flash eeprom module life (full temperature range) spec characteristic symbol min typical 1 1 typical endurance is evaluated at 25 o c. product qualification is performed to the minimum specification. for additional information on the freescale definition of typical endurance, please refer to engineering bulletin eb619, typical endurance for nonvolatile memory . unit 1 number of program/erase cycles per block for 16 kb and 64 kb blocks over the operating temperature range (t j ) p/e 100,000 ? cycles 2 number of program/erase cycles per block for 128 kb blocks over the operating temperature range (t j ) p/e 1,000 100,000 cycles 3 minimum data retention at 25 c ambient temperature 2 blocks with 0?1,000 p/e cycles blocks with 1,001?10,000 p/e cycles blocks with 10,001?100,000 p/e cycles 2 ambient temperature averaged over duration of applicati on, not to exceed product operating temperature range. retention 20 10 1?5 ?years table 22. pad ac specifications (5.0 v, 2.5 v) 1 spec pad type 2 src/dsc 3 output delay 4,4 (ns) rise/fall 5,6 (ns) load drive (pf) 1 slow 7 00 318/343 155/173 50 408/431 188/204 200 01 61/67 30/34 50 80/90 38/44 200 11 18/18 10/11 50 27/28 15/17 200 table 20. flash program and erase specifications 1 (continued) spec characteristic symbol min initial max 2 max 3 unit
electrical characteristics mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 41 2 medium 00 142/186 65/89 50 195/253 91/122 200 01 20/35 8.7/16.6 50 41/64 24/35 200 11 12/11 5.3/5.9 50 32/34 21/23 200 3 fast 8 00 2.7 1.5 10 01 20 10 30 11 50 4 input n/a 1.9/1.9 1.5/1.5 0.5 1 these are worst case values that are estimated from simulati on and not tested. the values in the table are simulated at f sys = 116 mhz, v dd = 1.08 ? 1.32 v, v dde = 1.62 ? 1.98 v, v ddeh =4.5?5.5v, v rc33 and v ddpll =3.0?3.6v, t a =t l to t h . 2 slow = sh or sha; medium = mh or mha; fast = f; input = iha. see ta bl e 2 . 3 src/dsc are bitfields in the pad confi guration registers. src?slew rate cont rol (slow and medium pad types only), dsc?drive strength control (fast pad type only). 4 this parameter is supplied for reference and is not guaranteed by design and not tested. 5 this parameter is guaranteed by characterization before qualification rather than 100% tested. 6 delay and rise/fall are measured to 20% or 80% of the respective signal. 7 add a maximum of one system clock to the output delay for delay with respect to system clock. 8 output delay is shown in figure 6 . add a maximum of one system clock to the output delay for delay with respect to system clock. table 23. de-rated pad ac specifications (3.3 v, 3.3 v) 1 spec pad type 2 src/dsc 3 out delay 4,5 (ns) rise/fall 6, (ns) load drive (pf) 1 slow 7 00 408/431 188/204 50 533/592 250/288 200 01 80/90 38/44 50 146/167 82/96 200 11 27/28 15/17 50 81/92 57/67 200 2 medium 00 184/240 79/107 50 253/330 114/153 200 01 28/47 11.8/21.8 50 58/88 34/49 200 11 18/17 7.6/8.9 50 46/51 30/35 200 table 22. pad ac specifications (5.0 v, 2.5 v) 1 (continued) spec pad type 2 src/dsc 3 output delay 4,4 (ns) rise/fall 5,6 (ns) load drive (pf)
mpc5668x microcontrolle r data sheet, rev. 5 electrical characteristics freescale semiconductor 42 figure 6. pad output delay 3 fast 8 00 2.5 1.2 10 01 1.2 20 10 1.2 30 11 1.2 50 4 input n/a 3/3 1.5/1.5 0.5 1 these are worst case values that are estimated from simulati on and not tested. the values in the table are simulated at f sys = 116 mhz, v dd = 1.08 ? 1.32 v, v dde =3.0?3.6v, v ddeh =3.0?3.6v, v rc33 and v ddpll = 3.0 ? 3.6 v, t a =t l to t h . 2 slow = sh or sha; medium = mh or mha; fast = f; input = iha. see ta bl e 2 . 3 src/dsc are bitfields in the pad confi guration registers. src?slew rate cont rol (slow and medium pad types only), dsc?drive strength control (fast pad type only). 4 this parameter is supplied for reference and is not guaranteed by design and not tested. 5 delay and rise/fall are measured to 20% or 80% of the respective signal. 6 this parameter is guaranteed by characterization before qualification rather than 100% tested. 7 add a maximum of one system clock to the output delay for delay with respect to system clock. 8 output delay is shown in figure 6 . add a maximum of one system clock to the output delay for delay with respect to system clock. table 23. de-rated pad ac specifications (3.3 v, 3.3 v) 1 (continued) spec pad type 2 src/dsc 3 out delay 4,5 (ns) rise/fall 6, (ns) load drive (pf) vdd/2 v oh v ol rising edge out delay falling edge out delay pad internal data input signal pad output
electrical characteristics mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 43 4.14 ac timing 4.14.1 reset and boot configuration pins figure 7. reset and boot configuration timing 4.14.2 external interrupt (irq) and no n-maskable interrupt (nmi) pins figure 8. irq and nmi timing table 24. reset and boot configuration timing spec characteristic symbol min max unit 1 reset pulse width t rpw 150 ? ns 2 bootcfg setup time after reset valid t rcsu ? 100 ? s 3 bootcfg hold time from reset valid t rch 0? ? s table 25. irq/nmi timing spec characteristic symbol min max unit 1 irq/nmi pulse width low t ipwl 3?t sys 2 irq/nmi pulse width high t ipwh 3?t sys 3 irq/nmi edge to edge time 1 1 applies when irq/nmi pins are configured for ri sing edge or falling edge events, but not both. t icyc 6?t sys 1 reset 3 bootcfg 2 irq/nmi 1,2 1,2 3
mpc5668x microcontrolle r data sheet, rev. 5 electrical characteristics freescale semiconductor 44 4.14.3 jtag (ieee 1149.1) interface figure 9. jtag test clock input timing table 26. jtag interface timing 1 1 these specifications apply to jtag boundary scan only. jtag timing specified at v dde =3.0?5.5v, t a =t l to t h , and c l = 30 pf with src = 0b11. spec characteristic symbol min max unit 1 tck cycle time t jcyc 100 ? ns 2 tck clock pulse width (measured at v dde /2) t jdc 40 60 ns 3 tck rise and fall times (40% ? 70%) t tckrise ?3ns 4 tms, tdi data setup time t tmss, t tdis 5?ns 5 tms, tdi data hold time t tmsh, t tdih 25 ? ns 6 tck low to tdo data valid t tdov ?25ns 7 tck low to tdo data invalid t tdoi 0?ns 8 tck low to tdo high impedance t tdohz ?20ns 9 jcomp assertion time t jcmppw 100 ? ns 10 jcomp setup time to tck low t jcmps 40 ? ns 11 tck falling edge to output valid t bsdv ?50ns 12 tck falling edge to output valid out of high impedance t bsdvz ?50ns 13 tck falling edge to output high impedance t bsdhz ?50ns 14 boundary scan input valid to tck rising edge t bsdst 50 ? ns 15 tck rising edge to boundary scan input invalid t bsdht 50 ? ns tck 1 2 2 3 3
electrical characteristics mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 45 figure 10. jtag test access port timing figure 11. jtag jcomp timing tck 4 5 6 7 8 tms, tdi tdo tck jcomp 9 10
mpc5668x microcontrolle r data sheet, rev. 5 electrical characteristics freescale semiconductor 46 figure 12. jtag boundary scan timing tck output signals input signals output signals 11 12 13 14 15
electrical characteristics mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 47 4.14.4 nexus debug interface figure 13. nexus output timing table 27. nexus debug port timing 1 1 jtag specifications in this table apply when used for debug func tionality. all nexus timing rela tive to mcko is measured from 50% of mcko and 50% of the respective signal. nexus timing specified at v dde =3.0?5.5v, t a =t l to t h , and c l =30pf with src = 0b11. spec characteristic symbol min max unit 1 mcko cycle time t mcyc 15.6 ? ns 2 mcko duty cycle t mdc 40 60 % 3 mcko low to mdo, mseo , evto data valid 2 2 mdo, mseo , and evto data is held valid until next mcko low cycle. t mdov ?0.1 0.25 t mcyc 4 evti pulse width t evtipw 4.0 ? t tcyc 5 evto pulse width t evtopw 1t mcyc 6 tck cycle time 3 3 the system clock frequency needs to be three times faster than the tck frequency. t tcyc 40 ? ns 7 tck duty cycle t tdc 40 60 % 8 tdi, tms data setup time t ntdis, t ntmss 8?ns 9 tdi, tms data hold time t ntdih, t ntmsh 5?ns 10 tck low to tdo data valid t jov 025ns 1 2 mcko mdo mseo evto output data valid 3 evti 4 5
mpc5668x microcontrolle r data sheet, rev. 5 electrical characteristics freescale semiconductor 48 figure 14. nexus tdi, tms, tdo timing tdo 8 9 tms, tdi 10 tck 6 7
electrical characteristics mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 49 4.14.5 enhanced modular i/o subsystem (emios) figure 15. emios timing table 28. emios timing 1 1 emios timing specified at v dde = 3.0 ? 5.5 v, t a =t l to t h , and cl = 30 pf with src = 0b11. spec characteristic symbol min max unit 1 emios input pulse width t mipw 4?t cyc 2 emios output pulse width t mopw 1 2 2 this specification does not include the rise and fall times. when calculating the minimum emios pulse width, include the rise and fall times defined in the slew rate control fiel ds (src) of the pad configuration registers (pcr). ?t cyc d_clkout 1 2 emios output emios input
mpc5668x microcontrolle r data sheet, rev. 5 electrical characteristics freescale semiconductor 50 4.14.6 deserial serial peripheral interface (dspi) table 29. dspi timing spec characteristic symbol 116 mhz 1 1 116 mhz timing specified at cl = 50 pf with src = 0b11. unit min. value max. value 1 dspi cycle time master (mtfe = 0) slave (mtfe = 0) master (mtfe = 1) slave (mtfe = 1) t sck 100 100 50 50 ? ? ? ? ns ns ns ns 2 pcs to sck delay 2 2 the maximum value is programmable in dspi_ctar n [pssck] and dspi_ctar n [cssck]. t csc 7?ns 3 after sck delay 3 3 the maximum value is programmable in dspi_ctar n [pasc] and dspi_ctar n [asc]. t asc 14 ? ns 4 sck duty cycle t sdc 0.4 ? t sck 0.6 ? t sck ns 5 slave access time (ss active to sout valid) t a ? 25 ns 6 slave sout disable time (ss inactive to sout high-z or invalid) t dis ? 25 ns 7 pcsx to pcss time t pcsc 0?ns 8pcss to pcsx time t pasc 0?ns 9 data setup time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 4 master (mtfe = 1, cpha = 1) 4 this number is calculated assuming the smpl_pt bitfield in dspi_mcr is set to 0b10. t sui 25 5 10 25 ? ? ? ? ns ns ns ns 10 data hold time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 4 master (mtfe = 1, cpha = 1) t hi ?4 7 12 ?4 ? ? ? ? ns ns ns ns 11 data valid (after sck edge) master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t suo ? ? ? ? 8 28 15 8 ns ns ns ns 12 data hold time for outputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t ho ?7 2 1 ?7 ? ? ? ? ns ns ns ns
electrical characteristics mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 51 figure 16. dspi classic spi timing ? master, cpha = 0 figure 17. dspi classic spi timing ? master, cpha = 1 data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol = 0) (cpol = 1) 3 2 pcsx sin sck output sck output (cpol = 0) (cpol = 1) sout data last data first data 12 11 10 last data data first data 9
mpc5668x microcontrolle r data sheet, rev. 5 electrical characteristics freescale semiconductor 52 figure 18. dspi classic spi timing ? slave, cpha = 0 figure 19. dspi classic spi timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1)
electrical characteristics mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 53 figure 20. dspi modified transfer format timing ? master, cpha = 0 figure 21. dspi modified transfer format timing ? master, cpha = 1 pcs x 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol = 0) (cpol = 1) pcs x 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol = 0) (cpol = 1)
mpc5668x microcontrolle r data sheet, rev. 5 electrical characteristics freescale semiconductor 54 figure 22. dspi modified transfer format timing ? slave, cpha = 0 figure 23. dspi modified transfer format timing ? slave, cpha = 1 figure 24. dspi pcs strobe (pcss ) timing last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) 12 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) pcs x 7 8 pcss
electrical characteristics mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 55 4.14.7 mlb interface 4.14.7.1 media local bus dc electrical characteristics table 30 provides the dc electri cal characteristics for the media local bus interface. table 30. media local bus dc electrical characteristics 4.14.7.2 media local bus (mlb) ac electrical characteristics table 31 and table 32 provide the ac electrical characteris tics for the media local bus interface. parameter symbol min typ max unit comments maximum input voltage ? ? ? 3.6 v low level input threshold v il ??0.7 v high level input threshold v ih 1.8 1 1 higher v ih thresholds can be used; however, t he risks associated with le ss noise margin in the syst em must be evaluated and assumed by the customer. ?? v low level output threshold v ol ??0.4 v i ol =6ma high level output threshold v oh 2.0 ? ? v i oh =?6ma input leakage current i l ??1 a 0 mpc5668x microcontrolle r data sheet, rev. 5 electrical characteristics freescale semiconductor 56 10 mlbsig/mlbdat output high impedance from mlbclk low t mcfdz 0?t mckl ns 11 bus hold time 3 t mdzh 4? ?ns 12 mlbsig/mlbdat output valid from mlbclk rising t mcrdv ?? 8ns ? ground = 0.0v ? load capacitance = 60 pf, siu_pcr144?siu_pcr146[dsc] = 0b11. ? mlb speed of 256 fs or 512 fs (fs = 48 khz) unless otherwise noted, all timi ng parameters are specified from the valid voltage threshold in ta bl e 3 0 . 1 the controller can shut off mlbclk to place mlb in a low-power state. 2 pulse width variation is measured at 1.25 v by triggering on one edge of mlbclk and measuring the spread on the other edge, measured in ns peak-to-peak (ns p-p). 3 the board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for thi s time period. therefore, coupling must be minimiz ed while meeting the maximum capacitive load listed. table 32. mlb timing for mlb speed 1024 fs spec parameter symbol min typ max unit comments 1 mlbclk operating frequency 1 f mck 45.056 ? ? ? ? 49.152 ? ? ? ? 49.2544 51.200 mhz 1024 fs at 44.0 khz 1024 fs at 48.0 khz 1024 fs at 48.1 khz 1024 fs pll unlocked 2 mlbclk rise time t mckr ?? 1nsv il to v ih 3 mlbclk fall time t mckf ?? 1nsv ih to v il 4 mlbclk cycle time t mckc ? 20.3 ? ns v il to v ih 5 mlbclk low time t mckl 6.5 6.1 7.7 7.3 ?ns1024fs pll unlocked 6 mlbclk high time t mckh 9.7 9.3 10.6 10.2 ?ns1024fs pll unclocked 7 mlbclk pulse width variation 2 t mpwv ? ? 0.7 ns p-p 8 mlbsig/mlbdat input valid to mlbclk falling t dsmcf 1? ?ns 9 mlbsig/mlbdat input hold from mlbclk low t dhmcf 0? ?ns 10 mlbsig/mlbdat output high impedance from mlbclk low t mcfdz 0?t mckl ns 11 bus hold time 3 t mdzh 2? ?ns 12 mlbsig/mlbdat output valid from mlbclk rising t mcrdv ?? 7ns ? ground = 0.0v ? load capacitance = 40 pf, siu_pcr144?siu_pcr146[dsc] = 0b00. ? mlb speed = 1024fs (fs = 48 khz) ? unless otherwise noted, timing parameters are specified from the valid voltage threshold in ta b l e 3 0 . table 31. mlb timing for mlb speed 256 fs or 512 fs (continued) spec parameter symbol min typ max unit comments
electrical characteristics mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 57 figure 25. media local bus (mlb) timing 4.14.8 fast ethernet interface mii signals use cmos signal levels compatible with devices oper ating at either 5.0 v or 3.3 v. signals are not ttl compatible. they follow the cmos elec trical characteristics. 4.14.8.1 mii receive signal timing (rxd [3:0], rx_dv, rx_er, and rx_clk) the receiver functions correctly up to a rx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requirement. in addition, the sy stem clock frequency must exceed four times the rx_clk frequency. 1 the controller can shut off mlbclk to place mlb in a low-power state. 2 pulse width variation is measured at 1.25 v by triggering on one edge of mlbclk and measuring the spread on the other edge, measured in ns peak-to-peak (ns p-p). 3 the board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for thi s time period. therefore, coupling must be minimiz ed while meeting the maximum capacitive load listed. table 33. mii receive signal timing spec characteristic min max unit m1 rxd[3:0], rx_dv, rx_er to rx_clk setup 5 ? ns m2 rx_clk to rxd[3:0], rx_dv, rx_er hold 5 ? ns m3 rx_clk pulse width high 35% 65% rx_clk period m4 rx_clk pulse width low 35% 65% rx_clk period mlbclk mlbsig/ 2 6 3 5 11 mlbdat (output) 10 4 valid data valid data mlbsig/ mlbdat (input) 9 8 12
mpc5668x microcontrolle r data sheet, rev. 5 electrical characteristics freescale semiconductor 58 figure 26. mii receive signal timing diagram 4.14.8.2 mii transmit signal timing (txd[3:0], tx_en, tx_er, tx_clk) the transmitter functions correctly up to a tx_clk maximu m frequency of 25 mhz +1%. there is no minimum frequency requirement. in addition, the sy stem clock frequency must exceed four times the tx_clk frequency. the transmit outputs (txd[3:0], tx_en, tx_er) can be programme d to transition from either the rising or falling edge of tx_clk, and the timing is the same in either case. this options allows the use of non-compliant mii phys. refer to the ethernet chapter for details of this option and how to enable it. figure 27. mii transmit signal timing diagram table 34. mii transmit signal timing 1 1 output pads configured with src = 0b11. spec characteristic min max unit m5 tx_clk to txd[3:0], tx_en, tx_er invalid 5 ? ns m6 tx_clk to txd[3:0], tx_en, tx_er valid ? 25 ns m7 tx_clk pulse width high 35% 65% tx_clk period m8 tx_clk pulse width low 35% 65% tx_clk period m1 m2 rx_clk (input) rxd[3:0] (inputs) rx_dv rx_er m3 m4 m6 tx_clk (input) txd[3:0] (outputs) tx_en tx_er m5 m7 m8
electrical characteristics mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 59 4.14.8.3 mii async inputs signal timing (crs and col) figure 28. mii async inputs timing diagram 4.14.8.4 mii serial management channel timing (mdio and mdc) the fec functions correctly with a maximum mdc frequency of 2.5 mhz. table 35. mii async inputs signal timing 1 1 output pads configured with src = 0b11. spec characteristic min max unit m9 crs, col minimum pulse width 1.5 ? tx_clk period table 36. mii serial management channel timing 1 1 output pads configured with src = 0b11. spec characteristic min max unit m10 mdc falling edge to mdio output invalid (minimum propagation delay) 0 ? ns m11 mdc falling edge to mdio output valid (max prop delay) ? 25 ns m12 mdio (input) to mdc rising edge setup 10 ? ns m13 mdio (input) to mdc rising edge hold 0 ? ns m14 mdc pulse width high 40% 60% mdc period m15 mdc pulse width low 40% 60% mdc period crs, col m9
mpc5668x microcontrolle r data sheet, rev. 5 electrical characteristics freescale semiconductor 60 figure 29. mii serial management channel timing diagram m11 mdc (output) mdio (output) m12 m13 mdio (input) m10 m14 m15
package characteristics mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 61 5 package characteristics 5.1 package mechanical data figure 30. 208 mapbga package mechanical drawing
mpc5668x microcontrolle r data sheet, rev. 5 package characteristics freescale semiconductor 62 figure 31. 208 mapbga package detail
package characteristics mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 63 figure 32. 256 mapbga package mechanical drawing
mpc5668x microcontrolle r data sheet, rev. 5 package characteristics freescale semiconductor 64 figure 33. 256 mapbga package detail
revision history mpc5668x microcontrolle r data sheet, rev. 5 freescale semiconductor 65 6 revision history table 37 describes the changes made to this document between revisions. table 37. revision history revision date description 0 april 2008 preliminary release. 1 june 2008 initial release: advance information. 2 jan 2009 release: advance information. 3 september 2009 release: advance information, interim updates. 4 january 2011 release: technical data, interim updates. 5 january 2011 release: technical data, interim updates.
document number: mpc5668x rev. 5 2010, 2011 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com freescale semiconductor literature distribution center 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2010, 2011. all rights reserved.

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